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MC68HC08AZ60A MC68HC08AZ48A
Advance Information
M68HC08
Microcontrollers
MC68HC08AZ60A/D Rev. 0, 2/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
MC68HC08AZ60A MC68HC08AZ48A
Technical Data -- Rev 0.0
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc.
(c) Motorola, Inc., 2001
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
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List of Paragraphs
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 27 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Section 3. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Section 4. ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Section 5. EEPROM-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 6. EEPROM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . 99 Section 8. System Integration Module (SIM) . . . . . . . . 117 Section 9. Clock Generator Module (CGM) . . . . . . . . . . 139 Section 10. Mask Options. . . . . . . . . . . . . . . . . . . . . . . . 167 Section 11. Break Module. . . . . . . . . . . . . . . . . . . . . . . . 171 Section 12. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 177 Section 13. Computer Operating Properly (COP) . . . . 189 Section 14. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . . 195 Section 15. External Interrupt Module (IRQ) . . . . . . . . . 201 Section 16. Serial Communications Interface (SCI) . . . 209
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List of Paragraphs Section 17. Serial Peripheral Interface (SPI). . . . . . . . . 249 Section 18. Timer Interface Module B (TIMB) . . . . . . . . 281 Section 19. Programmable Interrupt Timer (PIT) . . . . . 305 Section 20. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Section 21. MSCAN08 Controller (MSCAN08) . . . . . . . 343 Section 22. Keyboard Module (KBD) . . . . . . . . . . . . . . . 395 Section 23. Timer Interface Module A (TIMA) . . . . . . . . 403 Section 24. Analog-to-Digital Converter (ADC-15) . . . . 433 Section 25. Electrical Specifications. . . . . . . . . . . . . . . 445 Section 26. MC68HC08AZ60A Changes . . . . . . . . . . . . 461 Section 27. MC68HC08AZ48A Memory Map . . . . . . . . . 465 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
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Table of Contents
List of Paragraphs Table of Contents List of Figures List of Tables Section 1. General Description
1.1 1.2 1.3 1.4 1.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 2. Memory Map
2.1 2.2 2.3 2.4 2.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Additional Status and Control Registers . . . . . . . . . . . . . . . . . . 50 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . . . 52
Section 3. RAM
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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3.2 3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Section 4. ROM
4.1 4.2 4.3 4.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Section 5. EEPROM-1
5.1 5.2 5.3 5.4 5.5 5.6 5.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 61 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 EEPROM-1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . 69 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Section 6. EEPROM-2
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 EEPROM-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 81 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 EEPROM-2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . 89 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
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Section 7. Central Processor Unit (CPU)
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . .105 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 106 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Section 8. System Integration Module (SIM)
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 120 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 121 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Section 9. Clock Generator Module (CGM)
9.1 9.2 9.3 9.4
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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9.5 9.6 9.7 9.8 9.9 9.10 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 160 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .160
Section 10. Mask Options
10.1 10.2 10.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Section 11. Break Module
11.1 11.2 11.3 11.4 11.5 11.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Section 12. Monitor ROM (MON)
12.1 12.2 12.3 12.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Section 13. Computer Operating Properly (COP)
13.1
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
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13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .193 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 194
Section 14. Low Voltage Inhibit (LVI)
14.1 14.2 14.3 14.4 14.5 14.6 14.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 198 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Section 15. External Interrupt Module (IRQ)
15.1 15.2 15.3 15.4 15.5 15.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .206 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 206
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Table of Contents Section 16. Serial Communications Interface (SCI)
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 230 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Section 17. Serial Peripheral Interface (SPI)
17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Pin Name Conventions and I/O Register Addresses . . . . . . . 251 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
17.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 17.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .269 17.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 17.13 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
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Section 18. Timer Interface Module B (TIMB)
18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 293 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Section 19. Programmable Interrupt Timer (PIT)
19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .308 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Section 20. I/O Ports
20.1 20.2 20.3 20.4 20.5
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
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20.6 20.7 20.8 20.9 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
20.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Section 21. MSCAN08 Controller (MSCAN08)
21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . . 359 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360
21.10 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 21.11 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 21.12 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 21.13 Programmer's Model of Message Storage . . . . . . . . . . . . . . .368 21.14 Programmer's Model of Control Registers . . . . . . . . . . . . . . . 374
Section 22. Keyboard Module (KBD)
22.1 22.2 22.3 22.4
Advance Information 14 Table of Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
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22.5 22.6 22.7 22.8
Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .400 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Section 23. Timer Interface Module A (TIMA)
23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 418 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Section 24. Analog-to-Digital Converter (ADC-15)
24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
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Advance Information 15
Table of Contents Section 25. Electrical Specifications
25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 447 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 448 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 5.0 Vdc 0.5 V Serial Peripheral Interface (SPI) Timing . . . . 452 CGM Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 455
25.10 CGM Component Information. . . . . . . . . . . . . . . . . . . . . . . . . 456 25.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . 457 25.12 RAM Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 458 25.13 EEPROM Memory Characteristics . . . . . . . . . . . . . . . . . . . . . 458 25.14 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Section 26. MC68HC08AZ60A Changes
26.1 26.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 Significant Changes from the MC68HC08AZ60 (Non-A Suffix Device)461
Section 27. MC68HC08AZ48A Memory Map
27.1 27.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Glossary
Advance Information 16 Table of Contents
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Advance Information -- MC68HC08AZ60A
List of Figures
Figure 1-1 1-2 1-3 2-1 2-2 2-3 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 7-1 7-2 7-3 Title Page
MC68HC08AZ60A MCU Block Diagram . . . . . . . . . . . . . . . . . 30 64 QFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Memory Map (Continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 I/O Data, Status and Control Registers . . . . . . . . . . . . . . . . . . 45 Additional Status and Control Registers . . . . . . . . . . . . . . . . . . 50 EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 61 EEPROM-1 Control Register (EE1CR). . . . . . . . . . . . . . . . . . . 69 EEPROM-1 Array Configuration Register (EE1ACR). . . . . . . . 71 EEPROM-1 Nonvolatile Register (EE1NVR) . . . . . . . . . . . . . . 73 EE1DIV Divider High Register (EE1DIVH) . . . . . . . . . . . . . . . .74 EE1DIV Divider Low Register (EE1DIVL). . . . . . . . . . . . . . . . . 74 EEPROM-1 Divider Non-Volatile Register High (EE1DIVHNVR)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 EEPROM-1 Divider Non-Volatile Register Low (EE1DIVLNVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 EEPROM-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 81 EEPROM-2 Control Register (EE2CR). . . . . . . . . . . . . . . . . . . 89 EEPROM-2 Array Configuration Register (EE2ACR). . . . . . . . 91 EEPROM-2 Nonvolatile Register (EE2NVR) . . . . . . . . . . . . . . 93 EE2DIV Divider High Register (EE2DIVH) . . . . . . . . . . . . . . . .94 EE2DIV Divider Low Register (EE2DIVL). . . . . . . . . . . . . . . . . 94 EEPROM-2 Divider Non-Volatile Register High (EE2DIVHNVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 EEPROM-2 Divider Non-Volatile Register Low (EE2DIVLNVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MC68HC08AZ60A -- Rev 0.0 MOTOROLA List of Figures
Advance Information 17
List of Figures
7-4 7-5 7-6 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 9-1 9-2 9-3 9-4 9-5 9-6 10-1 10-2 11-1 11-2 11-3 12-1 12-2 12-3 12-4 12-5 12-6 13-1
Advance Information 18 List of Figures
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . 103 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 129 WAIT Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 WAIT Recovery From Interrupt or Break . . . . . . . . . . . . . . . . 132 WAIT Recovery From Internal Reset . . . . . . . . . . . . . . . . . . .132 STOP Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 STOP Mode Recovery From Interrupt . . . . . . . . . . . . . . . . . . 134 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 134 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 136 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 137 CGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .151 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 153 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . . 155 PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . . 157 Mask Option Register A (MORA) . . . . . . . . . . . . . . . . . . . . . . 168 Mask Option Register B (MORB) . . . . . . . . . . . . . . . . . . . . . . 170 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 173 Break Status and Control Register (BRKSCR). . . . . . . . . . . . 175 Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . . 176 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 187 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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List of Figures
13-2 14-1 14-2 15-1 15-2 15-3 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .193 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 198 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .202 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 206 SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 212 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . . . 217 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . 220 SCI I/O Receiver Register Summary . . . . . . . . . . . . . . . . . . .221 Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 232 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 235 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 237 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 239 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 243 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 245 SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Full-duplex Master-Slave Connections . . . . . . . . . . . . . . . . . . 255 Transmission Format (CPHA = `0'). . . . . . . . . . . . . . . . . . . . . 258 Transmission Format (CPHA = `1'). . . . . . . . . . . . . . . . . . . . . 258 Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 260 Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 262 Clearing SPRF When OVRF Interrupt is Not Enabled . . . . . . 263 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 266 SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . . 267 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 274 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .277 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Advance Information List of Figures 19
List of Figures
18-1 TIMB Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 18-2 TIMB I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 283 18-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 288 18-4 TIMB Status and Control Register (TBSC) . . . . . . . . . . . . . . .295 18-5 TIMB Counter Registers (TBCNTH and TBCNTL) . . . . . . . . . 297 18-6 TIMB Counter Modulo Registers (TBMODH and TBMODL) . 298 18-7 TIMB Channel Status and Control Registers (TBSC0-TBSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 18-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 18-9 TIMB Channel Registers (TBCH0H/L-TBCH1H/L) . . . . . . . . 304 19-1 PIT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 19-2 PIT I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 19-3 PIT Status and Control Register (PSC) . . . . . . . . . . . . . . . . . 310 19-4 PIT Counter Registers (PCNTH-PCNTL). . . . . . . . . . . . . . . . 312 19-5 PIT Counter Modulo Registers (PMODH-PMODL) . . . . . . . . 313 20-1 Port A data register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 20-2 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . . . . 318 20-3 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 20-4 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .320 20-5 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 321 20-6 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 20-7 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .323 20-8 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 324 20-9 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 20-10 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .326 20-11 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 327 20-12 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 20-13 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .329 20-14 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 332 20-15 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 20-16 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . . 334 20-17 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . . 335 20-18 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 20-19 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . . . .337 20-20 Data Direction Register G (DDRG). . . . . . . . . . . . . . . . . . . . . 338 20-21 Port G I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 20-22 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . .340 20-23 Data Direction Register H (DDRH) . . . . . . . . . . . . . . . . . . . . . 341
Advance Information 20 List of Figures MC68HC08AZ60A -- Rev 0.0 MOTOROLA
List of Figures
20-24 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 21-14 21-15 21-16 21-17 21-18 21-19 21-20 21-21 21-22 21-23 21-24 21-25 21-26 21-27 22-1 22-2 22-3 22-4 23-1 23-2 23-3 23-4 23-5
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Port H I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 User Model for Message Buffer Organization. . . . . . . . . . . . . 350 Single 32-Bit Maskable Identifier Acceptance Filter . . . . . . . .353 Dual 16-Bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . 354 Quadruple 8-Bit Maskable Acceptance Filters . . . . . . . . . . . .355 Sleep Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 362 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Segments Within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . 367 MSCAN08 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . 369 Receive/Transmit Message Buffer Extended Identifier (IDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .372 Transmit Buffer Priority Register (TBPR) . . . . . . . . . . . . . . . . 374 MSCAN08 Control Register Structure . . . . . . . . . . . . . . . . . . 375 Module Control Register 0 (CMCR0) . . . . . . . . . . . . . . . . . . .377 Module Control Register (CMCR1). . . . . . . . . . . . . . . . . . . . . 379 Bus Timing Register 0 (CBTR0) . . . . . . . . . . . . . . . . . . . . . . . 380 Bus Timing Register 1 (CBTR1) . . . . . . . . . . . . . . . . . . . . . . . 381 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . . . . . . 383 Receiver Interrupt Enable Register (CRIER) . . . . . . . . . . . . . 385 Transmitter Flag Register (CTFLG) . . . . . . . . . . . . . . . . . . . . 387 Transmitter Control Register (CTCR) . . . . . . . . . . . . . . . . . . . 388 Identifier Acceptance Control Register (CIDAC). . . . . . . . . . . 389 Receiver Error Counter (CRXERR) . . . . . . . . . . . . . . . . . . . . 391 Transmit Error Counter (CTXERR). . . . . . . . . . . . . . . . . . . . . 391 Identifier Acceptance Registers (CIDAR0-CIDAR3) . . . . . . . 392 Identifier Mask Registers (CIDMR0-CIDMR3) . . . . . . . . . . . . 393 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . 397 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 401 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 402 TIMA Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 TIMA I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 406 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 412 TIMA Status and Control Register (TASC) . . . . . . . . . . . . . . .420 TIMA Counter Registers (TACNTH and TACNTL) . . . . . . . . . 422
Advance Information List of Figures 21
List of Figures
23-6 23-7 23-8 23-9 24-1 24-2 24-3 24-4 25-1 25-2 25-5 27-1 TIMA Counter Modulo Registers (TAMODH and TAMODL) . 423 TIMA Channel Status and Control Registers (TASC0-TASC5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 TIMA Channel Registers (TACH0H/L-TACH5H/L) . . . . . . . . 430 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . 439 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .442 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .453 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 64-pin QFP (Case #840B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 Memory Map (Continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Advance Information 22 List of Figures
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
List of Tables
Table 1-1 1-2 1-3 1-4 2-1 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 7-1 7-2 8-1 8-2 8-3 8-4 9-1 9-2 9-3 11-1 12-1 12-2 12-3 12-4 12-5 12-6 Title Page
External Pins Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EEPROM-1 Array Address Blocks . . . . . . . . . . . . . . . . . . . . . . 64 Example Selective Bit Programming Description . . . . . . . . . . . 65 EEPROM-1 Program/Erase Mode Select. . . . . . . . . . . . . . . . . 70 EEPROM-1 Block Protect and Security Summary . . . . . . . . . . 72 EEPROM-2 Array Address Blocks . . . . . . . . . . . . . . . . . . . . . . 84 Example Selective Bit Programming Description . . . . . . . . . . . 85 EEPROM-2 Program/Erase Mode Select. . . . . . . . . . . . . . . . . 90 EEPROM-2 Block Protect and Security Summary . . . . . . . . . . 92 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Signal Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . . 143 Variable Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 VCO Frequency Multiplier (N) Selection. . . . . . . . . . . . . . . . . 158 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 173 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 183 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 183 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 184 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 184
MC68HC08AZ60A -- Rev 0.0 MOTOROLA List of Tables
Advance Information 23
List of Tables
12-7 12-8 13-1 14-1 14-2 15-1 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 17-1 17-2 17-3 17-4 17-5 18-1 18-2 19-1 19-2 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 21-1 21-2 21-3
Advance Information 24 List of Tables
READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .185 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 185 COP I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 190 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 SCI I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . 213 SCI Transmitter I/O Address Summary . . . . . . . . . . . . . . . . . 217 SCI Receiver I/O Address Summary . . . . . . . . . . . . . . . . . . .221 Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .234 SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . 247 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 I/O Register Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . 279 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .302 PIT I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . 307 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Port A pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Port G Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Port H Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 MSCAN08 Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . 359 MSCAN08 vs CPU Operating Modes . . . . . . . . . . . . . . . . . . . 360 Time segment syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
List of Tables
21-4 21-5 21-6 21-7 21-8 21-9 21-10 22-1 23-1 23-2 24-1 24-2
CAN Standard Compliant Bit Time Segment Settings . . . . . . 367 Data Length Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Synchronization Jump Width . . . . . . . . . . . . . . . . . . . . . . . . . 380 Baud Rate Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Time Segment Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Identifier Acceptance Mode Settings . . . . . . . . . . . . . . . . . . .390 Identifier Acceptance Hit Indication . . . . . . . . . . . . . . . . . . . . 390 I/O Register Address Summary . . . . . . . . . . . . . . . . . . . . . . . 397 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .428 Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
MC68HC08AZ60A -- Rev 0.0 MOTOROLA List of Tables
Advance Information 25
List of Tables
Advance Information 26 List of Tables
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 1. General Description
1.1 Contents
1.2 1.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.1 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . 32 1.4.2 Oscillator Pins (OSC1 and OSC2). . . . . . . . . . . . . . . . . . . 33 1.4.3 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4.4 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4.5 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . 33 1.4.6 Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4.7 ADC Analog Ground Pin (Avss/VREFL) . . . . . . . . . . . . . . . 33 1.4.8 ADC Reference High Voltage Pin (VREFH) . . . . . . . . . . . 34 1.4.9 ADC Analog Power Supply Pin (VDDAREF) . . . . . . . . . . . . 34 1.4.10 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . .34 1.4.11 Port A Input/Output (I/O) Pins (PTA7-PTA0) . . . . . . . . . . 34 1.4.12 Port B I/O Pins (PTB7/ATD7-PTB0/ATD0) . . . . . . . . . . . . 34 1.4.13 Port C I/O Pins (PTC5-PTC0) . . . . . . . . . . . . . . . . . . . . . . 34 1.4.14 Port D I/O Pins (PTD7-PTD0/ATD8) . . . . . . . . . . . . . . . . . 35 1.4.15 Port E I/O Pins (PTE7/SPSCK-PTE0/TxD) . . . . . . . . . . . . 35 1.4.16 Port F I/O Pins (PTF6-PTF0/TACH2). . . . . . . . . . . . . . . . . 35 1.4.17 Port G I/O Pins (PTG2/KBD2-PTG0/KBD0) . . . . . . . . . . . 35 1.4.18 Port H I/O Pins (PTH1/KBD4-PTH0/KBD3). . . . . . . . . . . . 36 1.4.19 CAN Transmit Pin (TxCAN) . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4.20 CAN Receive Pin (RxCAN). . . . . . . . . . . . . . . . . . . . . . . . . 36 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1.5.1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
MC68HC08AZ60A -- Rev 0.0 MOTOROLA General Description
Advance Information 27
General Description 1.2 Introduction
The MC68HC08AZ60A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
1.3 Features
Features of the MC68HC08AZ60A include the following: * * * * * * * * * * * * * * * High-Performance M68HC08 Architecture Fully Upward-Compatible Object Code with M6805, M146805, and M68HC05 Families 8.4MHz Internal Bus Frequency at 125C MSCAN08 Controller (Motorola Scalable CAN) (Implementing CAN 2.0b Protocol as Defined in BOSCH Specification Sep. 1991) Available in 64 QFP Package 61,744 Bytes User ROM User ROM Data security 1024 Bytes of On-Chip EEPROM with Security Feature 2048 Bytes of On-Chip RAM Serial Peripheral Interface (SPI) Module Serial Communications Interface (SCI) Module 16-bit Timer Interface Module (TIMA-6) with Six Input Capture/Output Compare Channels 16-bit Timer Interface Module (TIMB) with Two Input Capture/Output Compare Channels Programmable Interrupt Timer (PIT) Clock Generator Module (CGM)
Advance Information 28 General Description
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
General Description Features
* * *
8-Bit, 15-Channel Analog to Digital Convertor (ADC-15) 5-Bit Keyboard Interrupt Module System Protection Features - Computer Operating Properly (COP) with Optional Reset - Low-Voltage Detection with Optional Reset - Illegal Opcode Detection with Optional Reset - Illegal Address Detection with Optional Reset
* *
Low-Power Design (Fully Static with STOP and WAIT Modes) Master Reset Pin and Power-On Reset
Features of the CPU08 include the following: * * * * * * * * * * Enhanced HC05 Programming Model Extensive Loop ControlFunctions 16 Addressing Modes (8 more than the HC05) 16-Bit Index Register and Stack Pointer Memory-to-Memory Data Transfers Fast 8 x 8 Multiply Instruction Fast 16/8 Divide Instruction Binary-Coded Decimal (BCD) Instructions Optimization for Controller Applications `C' Language Support
Figure 1-1 shows the structure of the MC68HC08AZ60A
MC68HC08AZ60A -- Rev 0.0 MOTOROLA General Description
Advance Information 29
.
CPU REGISTERS
ARITHMETIC/LOGIC UNIT (ALU)
SERIAL COMMUNICATIONS INTERFACE MODULE RxCAN TxCAN MSCAN08 CONTROLLER MODULE BREAK MODULE LOW VOLTAGE INHIBIT MODULE
PTA
M68HC08 CPU
DDRA
DDRB
PTB
DDRC
USER RAM -- 2048 BYTES
PTC
DDRD
USER ROM -- 61,744 BYTES COMPUTER OPERATING PROPERLY MODULE TIMERA & B INTERFACE MODULES (6 + 2 Channels)
PTD
DDRE
CLOCK GENERATOR MODULE
SERIAL PERIPHERAL INTERFACE MODULE ANALOG TO DIGITAL CONVERTOR MODULE
RST
SYSTEM INTEGRATION MODULE IRQ MODULE POWER-ON RESET MODULE
PTE
DDRF
PROGRAMMABLE INTERRUPT TIMER MODULE KEYBOARD INTERRUPT MODULE
DDRG
PTF
VDD VSS VSSA VDDA POWER
DDRH
Figure 1-1. MC68HC08AZ60A MCU Block Diagram
PTH
VREFH AVSS/VREFL VDDAREF
PTG
30 General Description MOTOROLA
Advance Information
IRQ
General Description
PTA7-PTA0
PTB7/ATD7-PTB0/ATD0
CONTROL AND STATUS REGISTERS
PTC5-PTC3 PTC2/MCLK PTC1-PTC0 PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12/TBCLK PTD3/ATD11- PTD0/ATD8
USER EEPROM -- 1024 BYTES
MONITOR ROM -- 256 BYTES USER ROM VECTOR SPACE -- 52 BYTES OSC1 OSC2 CGMXFC
PTE7/SPSCK PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1- PTF4/TBCH0 PTF3/TACH5- PTF0/TACH2 PTG2/KBD2- PTG0/KBD0
MC68HC08AZ60A -- Rev 0.0
PTH1/KBD4- PTH0/KBD3
General Description Pin Assignments
1.4 Pin Assignments
Figure 1-2 shows the 64 QFP pin assignments.
PTD6/ATD14/TACLK
PTD4/ATD12/TBCLK 50
PTD5/ATD13
PTC2/MCLK
64
63
62
61
60
59
58
57
56
55
54
53
52
PTC4 IRQ RST PTF0/TACH2 PTF1/TACH3 PTF2/TACH4 PTF3/TACH5 PTF4/TBCH0 RxCAN TxCAN PTF5/TBCH1 PTF6 PTE0/TxD PTE1/RxD PTE2/TACH0 PTE3/TACH1
51
49
PTH1/KBD4
CGMXFC
VREFH
OSC1
OSC2
PTC5
PTC3
PTC1
PTC0
PTD7
VSSA
vDDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42
PTH0/KBD3 PTD3/ATD11 PTD2/ATD10 AVSS/VREFL VDDAREF PTD1/ATD9 PTD0/ATD8 PTB7/ATD7 PTB6/ATD6 PTB5/ATD5 PTB4/ATD4 PTB3/ATD3 PTB2/ATD2 PTB1/ATD1 PTB0/ATD0
MC68HC08AZ60A
41 40 39 38 37 36 35 34
18
19
20
21
22
23
24
25
26
27
28
29
30
PTE4/SS 17
31
16
33 PTA6 32
PTA7
PTG0/KBD0
PTG1/KBD1
PTG2/KBD2
PTA0
PTA1
PTA2
PTA3
PTA4
PTE5/MISO
PTE6/MOSI
Figure 1-2. 64 QFP Pin Assignments
MC68HC08AZ60A -- Rev 0.0 MOTOROLA General Description
PTE7/SPSCK
PTA5
VDD
VSS
Advance Information 31
General Description
1.4.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-3 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels.
MCU
VDD VSS
C1 0.1 F + C2
VDD
NOTE: Component values shown represent typical applications.
Figure 1-3. Power Supply Bypassing VSS is also the ground for the port output buffers and the ground return for the serial clock in the Serial Peripheral Interface Module (SPI). See Serial Peripheral Interface (SPI) on page 249.
NOTE:
VSS must be grounded for proper MCU operation.
Advance Information 32 General Description
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
General Description Pin Assignments
1.4.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Clock Generator Module (CGM) on page 139.
1.4.3 External Reset Pin (RST) A logic `0' on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. See System Integration Module (SIM) on page 117.
1.4.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. See External Interrupt Module (IRQ) on page 201.
1.4.5 Analog Power Supply Pin (VDDA) VDDA is the power supply pin for the analog portion of the Clock Generator Module (CGM). See Clock Generator Module (CGM) on page 139.
1.4.6 Analog Ground Pin (VSSA) VSSA is the ground connection for the analog portion of the Clock Generator Module (CGM). See Clock Generator Module (CGM) on page 139.
1.4.7 ADC Analog Ground Pin (Avss/VREFL) The AVSS/VREFL pin provides both the analog ground connection and the reference low voltage for the Analog-to-Digital Converter (ADC). See Analog-to-Digital Converter (ADC-15) on page 433.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA General Description
Advance Information 33
General Description
1.4.8 ADC Reference High Voltage Pin (VREFH) VREFH provides the reference high voltage for the Analog-to-Digital Converter (ADC). See Analog-to-Digital Converter (ADC-15) on page 433.
1.4.9 ADC Analog Power Supply Pin (VDDAREF) VDDAREF is the power supply pin for the analog portion of the Analog-toDigital Converter (ADC). See Analog-to-Digital Converter (ADC-15) on page 433.
1.4.10 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the Clock Generator Module (CGM). See Clock Generator Module (CGM) on page 139.
1.4.11 Port A Input/Output (I/O) Pins (PTA7-PTA0) PTA7-PTA0 are general-purpose bidirectional I/O port pins. See I/O Ports on page 315.
1.4.12 Port B I/O Pins (PTB7/ATD7-PTB0/ATD0) Port B is an 8-bit special function port that shares all eight pins with the Analog to Digital Convertor (ADC). See Analog-to-Digital Converter (ADC-15) on page 433 and I/O Ports on page 315.
1.4.13 Port C I/O Pins (PTC5-PTC0) PTC5-PTC3 and PTC1-PTC0 are general-purpose bidirectional I/O port pins. PTC2/MCLK is a special function port that shares its pin with the system clock. See I/O Ports on page 315.
Advance Information 34 General Description
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
General Description Pin Assignments
1.4.14 Port D I/O Pins (PTD7-PTD0/ATD8) Port D is an 8-bit special-function port that shares seven of its pins with the Analog-to-Digital Converter Module (ADC-15), one of its pins with the Timer Interface Module A (TIMA-6), and one more of its pins with the Timer Interface Module B (TIMB). See Timer Interface Module A (TIMA) on page 403 , Timer Interface Module B (TIMB) on page 281, Analog-to-Digital Converter (ADC-15) on page 433 and I/O Ports on page 315.
1.4.15 Port E I/O Pins (PTE7/SPSCK-PTE0/TxD) Port E is an 8-bit special function port that shares two of its pins with the Timer Interface Module A (TIMA), four of its pins with the Serial Peripheral Interface Module (SPI), and two of its pins with the Serial Communication Interface Module (SCI). See Serial Communications Interface (SCI) on page 209, Serial Peripheral Interface (SPI) on page 249, Timer Interface Module A (TIMA) on page 403 and I/O Ports on page 315.
1.4.16 Port F I/O Pins (PTF6-PTF0/TACH2) Port F is a 7-bit special function port that shares its pins with the Timer Interface Module B (TIMB). Six of its pins are shared with the Timer Interface Module A (TIMA-6). See Timer Interface Module A (TIMA) on page 403, Timer Interface Module B (TIMB) on page 281 and I/O Ports on page 315.
1.4.17 Port G I/O Pins (PTG2/KBD2-PTG0/KBD0) Port G is a 3-bit special function port that shares all of its pins with the Keyboard Module (KBD). See Keyboard Module (KBD) on page 395 and I/O Ports on page 315.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA General Description
Advance Information 35
General Description
1.4.18 Port H I/O Pins (PTH1/KBD4-PTH0/KBD3) Port H is a 2-bit special-function port that shares all of its pins with the Keyboard Module (KBD). See Keyboard Module (KBD) on page 395 and I/O Ports on page 315.
1.4.19 CAN Transmit Pin (TxCAN) TxCAN is the digital output from the MSCAN08 module. See MSCAN08 Controller (MSCAN08) on page 343.
1.4.20 CAN Receive Pin (RxCAN) RxCAN is the digital input to the MSCAN08 module. See MSCAN08 Controller (MSCAN08) on page 343. Table 1-1. External Pins Summary
PIN NAME PTA7 - PTA0 PTB7/ATD7 - PTB0/ATD0 PTC5 - PTC0 PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12/TBCLK PTD3/ATD11-PTD0/A TD8 PTE7/SPSCK PTE6/MOSI PTE5/MISO FUNCTION General Purpose I/O General Purpose I/0 / ADC channel General Purpose I/O General Purpose I/O General Purpose I/O/ADC Channel/Timer A External Input clock General Purpose I/O/ADC Channel General Purpose I/O /ADC Channel/Timer B External Input Clock General Purpose I/O /ADC channel General Purpose I/0 / SPI clock General Purpose I/0 / SPI data path General Purpose I/0 / SPI data path DRIVER TYPE Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State (open drain) Dual State (open drain) Dual State (open drain) No No No No Yes (only for Timer A function) No Yes (only for Timer B function) No Yes (only for SPI function) Yes (only for SPI function) Yes (only for SPI function) HYSTERESIS(1) RESET STATE Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z)
Advance Information 36 General Description
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
General Description Pin Assignments
Table 1-1. External Pins Summary (Continued)
PIN NAME PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1 PTF4/TBCH0 PTF3/TACH5 PTF2/TACH4 PTF1/TACH3 PTF0/TACH2 PTG2/KBD2 - PTG0/KBD0 PTH1/KBD4- PTH0/KBD3 VDD VSS VDDA VSSA VREFH AVSS/VREFL FUNCTION General Purpose I/0 / SPI Slave Select General Purpose I/0 / TimerA channel 1 General Purpose I/0 / TimerA channel 0 General Purpose I/0 / SCI Receive Data General Purpose I/0 / SCI Transmit Data General Purpose I/O General Purpose I/O /Timer B Channel 1 General Purpose I/0 / Timer B Channel 0 General Purpose I/0/Timer A Channel 5 General Purpose I/0/Timer A Channel 4 General Purpose I/0 /Timer A Channel 3 General Purpose I/0 /Timer A channel 2 General Purpose I/0/Keyboard Wakeup Pin General Purpose I/0/Keyboard Wakeup Pin Logical Chip Power Supply Logical Chip Ground CGM Analog Power Supply CGM Analog Ground ADC Reference High Voltage ADC Gnd & Reference Low Voltage DRIVER TYPE Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State Dual State NA NA NA NA NA NA HYSTERESIS(1) Yes (only for SPI function) Yes (only for Timer A function) Yes (only for Timer A function) Yes (only for SCI function) No No Yes (only for Timer B function) Yes (only for Timer B function) Yes (only for Timer A function) Yes (only for Timer A function) Yes (only for Timer A function) Yes (only for Timer A function) Yes (only for KBD function) Yes (only for KBD function) NA NA NA NA NA NA RESET STATE Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) NA NA NA NA NA NA
MC68HC08AZ60A -- Rev 0.0 MOTOROLA General Description
Advance Information 37
General Description
Table 1-1. External Pins Summary (Continued)
PIN NAME VDDAREF OSC1 OSC2 CGMXFC IRQ RST RxCAN TxCAN FUNCTION ADC Power supply External Clock In External Clock Out PLL Loop Filter Cap External Interrupt Request Reset MSCAN08 Serial Input MSCAN08 Serial Output DRIVER TYPE NA NA NA NA NA NA NA Output NA YES NA NA YES YES YES NA HYSTERESIS(1) RESET STATE NA Input (Hi-Z) Output NA Input (Hi-Z) Input (Hi-Z) Input (Hi-Z) Output
1. Hysteresis is not 100% tested but is typically a minimum of 300mV.
Details of the clock connections to each of the modules on the MC68HC08AZ60A are shown in Table 1-3. A short description of each clock source is also given in Table 1-2. Table 1-2. Signal Name Conventions
Signal name CGMXCLK CGMOUT Bus Clock SPSCK TACLK TBCLK Description Buffered version of OSC1 from Clock Generator Module (CGM) PLL-based or OSC1-based clock output from Clock Generator Module (CGM) CGMOUT divided by two SPI serial clock External clock Input for TIMA External clock Input for TIMB
Table 1-3. Clock Source Summary
Module ADC MSCAN08 COP CPU CGMXCLK or Bus Clock CGMXCLK or CGMOUT CGMXCLK Bus Clock Clock source
Advance Information 38 General Description
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
General Description Ordering Information
Table 1-3. Clock Source Summary (Continued)
Module EEPROM ROM RAM SPI SCI TIMA TIMB PIT KBI SIM IRQ BRK LVI CGM CGMXCLK or Bus Clock Bus Clock Bus Clock Bus Clock/SPSCK CGMXCLK Bus Clock or PTD6/ATD14/TACLK Bus Clock or PTD4/ATD12/TBCLK Bus Clock Bus Clock CGMOUT and CGMXCLK Bus Clock Bus Clock Bus Clock OSC1 and OSC2 Clock source
1.5 Ordering Information
This section contains instructions for ordering the MC68HC08AZ60A.
1.5.1 MC Order Numbers Table 1-4. MC Order Numbers
MC Order Number
MC68HC08AZ60ACFU MC68HC08AZ60AVFU MC68HC08AZ60AMFU
Operating Temperature Range
- 40 C to + 85C - 40 C to + 105 C - 40 C to + 125 C
MC68HC08AZ60A -- Rev 0.0 MOTOROLA General Description
Advance Information 39
General Description
Advance Information 40 General Description
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 2. Memory Map
2.1 Contents
2.2 2.3 2.4 2.5 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Additional Status and Control Registers . . . . . . . . . . . . . . . 50 Vector Addresses and Priority . . . . . . . . . . . . . . . . . . . . . . . 52
2.2 Introduction
The CPU08 can address 64K bytes of memory space. The memory map, shown in Figure 2-1, includes: * * * * * 61,744 Bytes of ROM 2048 Bytes of RAM 1024 Bytes of EEPROM with Protect Option 52 Bytes of User-Defined Vectors 256 Bytes of Monitor ROM
The following definitions apply to the memory map representation of reserved and unimplemented locations. * * Reserved -- Accessing a reserved location can have unpredictable effects on MCU operation. Unused -- These locations are reserved in the memory map for future use, accessing an unused location can have unpredictable effects on MCU operation.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Memory Map
Advance Information 41
Memory Map
* Unimplemented -- Accessing an unimplemented location can cause an illegal address reset (within the constraints as outlined in the System Integration Module (SIM)). MC68HC08AZ60A
$0000 $004F $0050 $044F $0450 $04FF $0500 $057F $0580 $05FF $0600 $07FF $0800 $09FF $0A00 $0DFF $0E00 $7FFF $8000 $FDFF $FE00 $FE01 $FE02 $FE03 I/O REGISTERS (80 BYTES)
RAM-1, 1024 BYTES
ROM-2, 176 BYTES
CAN CONTROL AND MESSAGE BUFFERS, 128 BYTES
ROM-2, 128 BYTES
EEPROM-2, 512 BYTES
EEPROM-1, 512 BYTES
RAM-2 , 1024 BYTES
ROM-2, 29,184 BYTES
ROM-1, 32,256 BYTES SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR) RESERVED SIM BREAK FLAG CONTROL REGISTER (SBFCR)
Advance Information 42 Memory Map
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Memory Map Introduction
MC68HC08AZ60A
$FE04 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FE11 $FE12 $FE19 $FE1A $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 $FF1F $FF20 $FF6F $FF70 $FF71 $FF72 $FF79 $FF7A RESERVED (5 BYTES) MASK OPTION REGISTER B (MORB) RESERVED RESERVED BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BSCR) LVI STATUS REGISTER (LVISR) EEPROM-1EEDIVH NON-VOLATILE REGISTER (EE1DIVHNVR) EEPROM-1EEDIVL NON-VOLATILE REGISTER (EE1DIVLNVR) RESERVED (8 BYTES) EEPROM-1 EE DIVIDER HIGH REGISTER (EE1DIVH) EEPROM-1 EE DIVIDER LOW REGISTER (EE1DIVL) EEPROM-1 EEPROM NON-VOLATILE REGISTER (EE1NVR) EEPROM-1 EEPROM CONTROL REGISTER (EE1CR) RESERVED EEPROM-1 EEPROM ARRAY CONFIGURATION REGISTER (EE1ACR) MONITOR ROM (256 BYTES)
UNIMPLEMENTED (80 BYTES) EEPROM-2 EEDIVH NON-VOLATILE REGISTER (EE2DIVHNVR) EEPROM-2 EEDIVL NON-VOLATILE REGISTER (EE2DIVLNVR) RESERVED (8 BYTES) EEPROM-2 EE DIVIDER HIGH REGISTER (EE2DIVH)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Memory Map
Advance Information 43
Memory Map
MC68HC08AZ60A
$FF7B $FF7C $FF7D $FF7E $FF7F $FF80 $FFCB $FFCC $FFFF EEPROM-2 EE DIVIDER LOW REGISTER (EE2DIVL) EEPROM-2 EEPROM NON-VOLATILE REGISTER (EE2NVR) EEPROM-2 EEPROM CONTROL REGISTER (EE2CR) RESERVED EEPROM-2 EEPROM ARRAY CONFIGURATION REGISTER (EE2ACR) RESERVED (76 BYTES)
VECTORS (52 BYTES) See Table 2-1 on page 52
Figure 2-1. Memory Map (Continued)
Advance Information 44 Memory Map
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Memory Map I/O Section
2.3 I/O Section
Addresses $0000-$004F, shown in Figure 2-2, contain the I/O Data, Status and Control Registers.
Addr. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F Register Name Port A Data Register (PTA) Port B Data Register (PTB) Port C Data Register (PTC) Port D Data Register (PTD) Read: Write: Read: Write: Read: Write: Read: Write: PTD7 PTD6 DDRA6 DDRB6 0 Bit 7 PTA7 PTB7 0 6 PTA6 PTB6 0 5 PTA5 PTB5 PTC5 PTD5 DDRA5 DDRB5 DDRC5 DDRD5 PTE5 PTF5 0 0 4 PTA4 PTB4 PTC4 PTD4 DDRA4 DDRB4 DDRC4 DDRD4 PTE4 PTF4 0 0 3 PTA3 PTB3 PTC3 PTD3 DDRA3 DDRB3 DDRC3 DDRD3 PTE3 PTF3 0 0 2 PTA2 PTB2 PTC2 PTD2 DDRA2 DDRB2 DDRC2 DDR2 PTE2 PTF2 PTG2 0 1 PTA1 PTB1 PTC1 PTD1 DDRA1 DDRB1 DDRC1 DDRD1 PTE1 PTF1 PTG1 PTH1 DDRE1 DDRF1 DDRG1 DDRH1 Bit 0 PTA0 PTB0 PTC0 PTD0 DDRA0 DDRB0 DDRC0 DDRD0 PTE0 PTF0 PTG0 PTH0 DDRE0 DDRF0 DDRG0 DDRH0
Data Direction Register A Read: DDRA7 (DDRA) Write: Data Direction Register B Read: DDRB7 (DDRB) Write: Data Direction Register C Read: MCLKE (DDRC) Write: N Data Direction Register D Read: DDRD7 (DDRD) Write: Port E Data Register (PTE) Port F Data Register (PTF) Port G Data Register (PTG) Port H Data Register (PTH) Read: Write: Read: Write: Read: Write: Read: Write: 0 0 PTE7 0
DDRD6 PTE6 PTF6 0 0
Data Direction Register E Read: DDRE7 (DDRE) Write: Data Direction Register F Read: (DDRF) Write: Data Direction Register G Read: (DDRG) Write: Data Direction Register H Read: (DDRH) Write: 0 0 0
DDRE6 DDRF6 0 0
DDRE5 DDRF5 0 0
DDRE4 DDRF4 0 0
DDRE3 DDRF3 0 0
DDRE2 DDRF2 DDRG2 0
Figure 2-2. I/O Data, Status and Control Registers (Sheet 1 of 5)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Memory Map Advance Information 45
Memory Map
Addr. $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021
Register Name SPI Control Register (SPCR) Read: Write:
Bit 7 SPRIE SPRF R7 T7 LOOPS SCTIE R8 SCTE 0 R7 T7 0 0 0
6 R ERRIE R6 T6 ENSCI TCIE T8 TC 0 R6 T6 0 0 0 PLLF LOCK
5 SPMSTR OVRF R5 T5 TXINV SCRIE R SCRF 0 R5 T5 SCP1 0 0
4 CPOL MODF R4 T4 M ILIE R IDLE 0 R4 T4 SCP0 0 0
3 CPHA SPTE R3 T3 WAKE TE ORIE OR 0 R3 T3 R IRQF KEYF 1 0
2 SPWOM MODFE N R2 T2 ILTY RE NEIE NF 0 R2 T2 SCR2 0 ACK 0 ACKK 1 0
1 SPE SPR1 R1 T1 PEN RWU FEIE FE BKF R1 T1 SCR1 IMASK
Bit 0 SPTIE SPR0 R0 T0 PTY SBK PEIE PE RPF R0 T0 SCR0 MODE
SPI Status and Control Read: Register (SPSCR) Write: SPI Data Register (SPDR) SCI Control Register 1 (SCC1) SCI Control Register 2 (SCC2) SCI Control Register 3 (SCC3) SCI Status Register 1 (SCS1) SCI Status Register 2 (SCS2) SCI Data Register (SCDR) SCI Baud Rate Register (SCBR) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
IRQ Status and Control Read: Register (ISCR) Write: Keyboard Status and Control Read: Register (KBSCR) Write: PLL Control Register (PCTL) Read: Write:
IMASKK MODEK 1 0 1 0
PLLIE AUTO MUL7
PLLON ACQ MUL5
BCS XLD MUL4
PLL Bandwidth Control Read: Register (PBWC) Write: PLL Programming Register Read: (PPG) Write: Mask Option Register A (MORA) Write:
MUL6
VRS7
VRS6 COPRS
VRS5 STOP
VRS4 COPD
Read: LVISTOP ROMSEC LVIRST TOF 0 0
LVIPWR SSREC 0 TRST KBIE4 0 R KBIE3
Timer A Status and Control Read: Register (TASC) Write: Keyboard Interrupt Enable Read: Register (KBIER) Write:
TOIE 0
TSTOP 0
PS2 KBIE2
PS1 KBIE1
PS0 KBIE0
Figure 2-2. I/O Data, Status and Control Registers (Sheet 2 of 5)
Advance Information 46 Memory Map MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Memory Map I/O Section
Addr. $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 $0032 $0033
Register Name Timer A Counter Register Read: High (TACNTH) Write: Timer A Counter Register Read: Low (TACNTL) Write: Timer A Modulo Register Read: High (TAMODH) Write: Timer A Modulo Register Read: Low (TAMODL) Write: Timer A Channel 0 Status and Read: Control Register (TASC0) Write: Timer A Channel 0 Register Read: High (TACH0H) Write: Timer A Channel 0 Register Read: Low (TACH0L) Write: Timer A Channel 1 Status and Read: Control Register (TASC1) Write: Timer A Channel 1 Register Read: High (TACH1H) Write: Timer A Channel 1 Register Read: Low (TACH1L) Write: Timer A Channel 2 Status and Read: Control Register (TASC2) Write: Timer A Channel 2 Register Read: High (TACH2H) Write: Timer A Channel 2 Register Read: Low (TACH2L) Write: Timer A Channel 3 Status and Read: Control Register (TASC3) Write: Timer A Channel 3 Register Read: High (TACH3H) Write: Timer A Channel 3 Register Read: Low (TACH3L) Write: Timer A Channel 4 Status and Read: Control Register (TASC4) Write: Timer A Channel 4 Register High Read: (TACH4H) Write:
Bit 7 Bit 15 Bit 7
6 14 6
5 13 5
4 12 4
3 11 3
2 10 2
1 9 1
Bit 0 Bit 8 Bit 0
Bit 15 Bit 7 CH0F 0 Bit 15 Bit 7 CH1F 0 Bit 15 Bit 7 CH2F 0 Bit 15 Bit 7 CH3F 0 Bit 15 Bit 7 CH4F 0 Bit 15
14 6 CH0IE 14 6 CH1IE 14 6 CH2IE 14 6 CH3IE 14 6 CH4IE 14
13 5 MS0B 13 5 0 R 13 5 MS2B 13 5 0 R 13 5 MS4B 13
12 4 MS0A 12 4 MS1A 12 4 MS2A 12 4 MS3A 12 4 MS4A 12
11 3 ELS0B 11 3 ELS1B 11 3 ELS2B 11 3 ELS3B 11 3 ELS4B 11
10 2 ELS0A 10 2 ELS1A 10 2 ELS2A 10 2 ELS3A 10 2 ELS4A 10
9 1 TOV0 9 1 TOV1 9 1 TOV2 9 1 TOV3 9 1 TOV4 9
Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 CH2MAX Bit 8 Bit 0 CH3MAX Bit 8 Bit 0 CH4MAX Bit 8
Figure 2-2. I/O Data, Status and Control Registers (Sheet 3 of 5)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Memory Map Advance Information 47
Memory Map
Addr. $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F $0040 $0041 $0042 $0043 $0044 $0045
Register Name Timer A Channel 4 Register Low Read: (TACH4L) Write: Timer A Channel 5 Status and Read: Control Register (TASC5) Write: Timer A Channel 5 Register Read: High (TACH5H) Write: Timer A Channel 5 Register Read: Low (TACH5L) Write: Analog-to-Digital Status and Read: Control Register (ADSCR) Write: Analog-to-Digital Data Register Read: (ADR) Write: Analog-to-Digital Input Clock Read: Register (ADICLK) Write: Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Bit 7 Bit 7 CH5F 0 Bit 15 Bit 7 COCO R AD7 R ADIV2
6 6 CH5IE 14 6 AIEN AD6 R ADIV1
5 5 0 R 13 5 ADCO AD5 R ADIV0
4 4 MS5A 12 4 ADCH4 AD4 R ADICLK
3 3 ELS5B 11 3 ADCH3 AD3 R 0 R
2 2 ELS5A 10 2 ADCH2 AD2 R 0 R
1 1 TOV5 9 1 ADCH1 AD1 R 0 R
Bit 0 Bit 0 CH5MAX Bit 8 Bit 0 ADCH0 AD0 R 0 R
Timer B Status and Control Read: Register (TBSCR) Write: Timer B Counter Register High Read: (TBCNTH) Write: Timer B Counter Register Low Read: (TBCNTL) Write: Timer B Modulo Register High Read: (TBMODH) Write: Timer B Modulo Register Low Read: (TBMODL) Write: Timer B CH0 Status and Control Read: Register (TBSC0) Write:
TOF 0 Bit 15 Bit 7
TOIE 14 6
TSTOP 13 5
0 TRST 12 4
0 R 11 3
PS2 10 2
PS1 9 1
PS0 Bit 8 Bit 0
Bit 15 Bit 7 CH0F 0
14 6 CH0IE
13 5 MS0B
12 4 MS0A
11 3 ELS0B
10 2 ELS0A
9 1 TOV0
Bit 8 Bit 0 CH0MAX
Figure 2-2. I/O Data, Status and Control Registers (Sheet 4 of 5)
Advance Information 48 Memory Map MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Memory Map I/O Section
Addr. $0046 $0047
Register Name Timer B CH0 Register High Read: (TBCH0H) Write: Timer B CH0 Register Low Read: (TBCH0L) Write: Timer B CH1 Status and Control Read: Register (TBSC1) Write: Timer B CH1 Register High Read: (TBCH1H) Write: Timer B CH1 Register Low Read: (TBCH1L) Write: PIT Status and Control Register Read: (PSC) Write: PIT Counter Register High Read: (PCNTH) Write: PIT Counter Register Low Read: (PCNTL) Write: PIT Modulo Register High Read: (PMODH) Write: PIT Modulo Register Low Read: (PMODL) Write:
Bit 7 Bit 15 Bit 7 CH1F 0 Bit 15 Bit 7 POF 0 Bit 15 Bit 7
6 14 6 CH1IE 14 6 POIE 14 6
5 13 5 0 R 13 5 PSTOP 13 5
4 12 4 MS1A 12 4 0 PRST 12 4
3 11 3 ELS1B 11 3 0 11 3
2 10 2 ELS1A 10 2 PPS2 10 2
1 9 1 TOV1 9 1 PPS1 9 1
Bit 0 Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 PPS0 Bit 8 Bit 0
$0048 $0049 $004A $004B $004C $004D $004E $004F
Bit 15 Bit 7
14 6
13 5
12 4
11 3
10 2
9 1
Bit 8 Bit 0
= Unimplemented
R
= Reserved
Figure 2-2. I/O Data, Status and Control Registers (Sheet 5 of 5)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Memory Map
Advance Information 49
Memory Map 2.4 Additional Status and Control Registers
Selected addresses in the range $FE00 to $FFCB contain additional Status and Control registers as shown in Figure 2-3. A noted exception is the COP Control Register (COPCTL) at address $FFFF.
Addr. $FE00 Register Name SIM Break Status Register Read: (SBSR) Write: Read: Write: BCFE R 0 R R R R 0 R 0 R 0 Bit 7 R POR 6 R PIN 5 R COP 4 R ILOP 3 R ILAD 2 R 0 1 BW 0 LVI Bit 0 R 0
$FE01 SIM Reset Status Register (SRSR) $FE03 $FE09 $FE0C $FE0D $FE0E $FE0F $FE10 $FE11 $FE1A $FE1B
SIM Break Flag Control Register Read: (SBFCR) Write: Mask Options Register B (MORB) Write:
Read: EEDIVCLK
EESEC EEMONSEC AZ60A
Break Address Register High Read: (BRKH) Write: Break Address Register Low Read: (BRKL) Write: Break Status and Control Read: Register (BRKSCR) Write: LVI Status Register (LVISR) Write:
Bit 15 Bit 7 BRKE
14 6 BRKA 0
13 5 0 0
12 4 0 0
11 3 0 0
10 2 0 0
9 1 0 0
Bit 8 Bit 0 0 0
Read: LVIOUT
EE1DIV Hi Non-volatile Register Read: EEDIVSECD (EE1DIVHNVR) Write: EE1DIV Lo Non-volatile Register Read: EEDIV7 (EE1DIVLNVR) Write: EE1DIV Divider High Register Read: EEDIVSECD (EE1DIVH) Write: EE1DIV Divider Low Register Read: EEDIV7 (EE1DIVL) Write:
R EEDIV6 0
R EEDIV5 0
R EEDIV4 0
R EEDIV3 0
EEDIV10 EEDIV9 EEDIV2 EEDIV1
EEDIV8 EEDIV0 EEDIV8 EEDIV0 EEBP0 EEPGM EEBP0
EEDIV10 EEDIV9 EEDIV2 EEBP2 EELAT EEBP2 EEDIV1 EEBP1 AUTO EEBP1
EEDIV6
EEDIV5
EEDIV4
EEDIV3
$FE1C $FE1D $FE1F
EEPROM-1 Nonvolatile Register Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 (EE1NVR) Write: EEPROM-1 Control Register Read: UNUSED (EE1CR) Write: 0 EEOFF EERAS1 EERAS0
EEPROM-1 Array Configuration Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 Register (EE1ACR) Write:
Figure 2-3. Additional Status and Control Registers (Sheet 1 of 2)
Advance Information 50 Memory Map
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Memory Map Additional Status and Control Registers
Addr. $FF70 $FF71 $FF7A $FF7B
Register Name
Bit 7
6 R EEDIV6 0
5 R EEDIV5 0
4 R EEDIV4 0
3 R EEDIV3 0
2
1
Bit 0 EEDIV8 EEDIV0 EEDIV8 EEDIV0 EEBP0 EEPGM EEBP0
EE2DIV Hi Non-volatile Register Read: EEDIVSECD (EE2DIVHNVR) EE2DIV Lo Non-volatile Register Read: (EE2DIVLNVR) EE2DIV Divider High Register Read: (EE2DIVH) EE2DIV Divider Low Register Read: (EE2DIVL) EEDIV7
EEDIVSECD
EEDIV10 EEDIV9 EEDIV2 EEDIV1
EEDIV10 EEDIV9 EEDIV2 EEBP2 EELAT EEBP2 EEDIV1 EEBP1 AUTO EEBP1
EEDIV7
EEDIV6
EEDIV5
EEDIV4
EEDIV3
$FE7C $FE7D $FE7F
EEPROM-2 Nonvolatile Register Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 (EE2NVR) Write: EEPROM-2 Control Register Read: UNUSED (EE2CR) Write: 0 EEOFF EERAS1 EERAS0
EEPROM-2 Array Configuration Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 Register (EE2ACR) Write: Read: Write:
$FFFF
COP Control Register (COPCTL)
LOW BYTE OF RESET VECTOR WRITING TO $FFFF CLEARS COP COUNTER = Unimplemented R = Reserved
Figure 2-3. Additional Status and Control Registers (Sheet 2 of 2)
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Memory Map 2.5 Vector Addresses and Priority
Addresses in the range $FFCC to $FFFF contain the user-specified vector locations. The vector addresses are shown inTable 2-1.
Table 2-1. Vector addresses (1)
Address Vector TIMA Channel 5 Vector (high) TIMA Channel 5 Vector (low) TIMA Channel 4 Vector (high) TIMA Channel 4 Vector (low) ADC Vector (high) ADC Vector (low) Keyboard Vector (high) Keyboard Vector (low) SCI Transmit Vector (high) SCI Transmit Vector (Low) SCI Receive Vector (High) SCI Receive Vector (Low) SCI Error Vector (High) SCI Error Vector (Low) MSCAN08 Transmit Vector (High) MSCAN08 Transmit Vector (Low) MSCAN08 Receive Vector (High) MSCAN08 Receive Vector (Low) MSCAN08 Error Vector (High) MSCAN08 Error Vector (Low) MSCAN08 Wakeup Vector (High) MSCAN08 Wakeup Vector (Low)
Lowest Priority
$FFCC $FFCD $FFCE $FFCF $FFD0 $FFD1 $FFD2 $FFD3 $FFD4 $FFD5 $FFD6 $FFD7 $FFD8 $FFD9 $FFDA $FFDB $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1
Advance Information 52 Memory Map
Priority
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Memory Map Vector Addresses and Priority
Table 2-1. Vector addresses (Continued)(1)
Address $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE Vector SPI Transmit Vector (High) SPI Transmit Vector (Low) SPI Receive Vector (High) SPI Receive Vector (Low) TIMB Overflow Vector (High) TIMB Overflow Vector (Low) TIMB CH1 Vector (High) TIMB CH1 Vector (Low) TIMB CH0 Vector (High) TIMB CH0 Vector (Low) TIMA Overflow Vector (High) TIMA Overflow Vector (Low) TIMA CH3 Vector (High) TIMA CH3 Vector (Low) TIMA CH2 Vector (High) TIMA CH2 Vector (Low) TIMA CH1 Vector (High) TIMA CH1 Vector (Low) TIMA CH0 Vector (High) TIMA CH0 Vector (Low) PIT Vector (High) PIT Vector (Low) PLL Vector (High) PLL Vector (Low) IRQ Vector (High) IRQ Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low)
Priority
$FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE
Highest Priority
$FFFF
1. All available ROM locations not defined by the user will by default be filled with the software interrupt (SWI, opcode 83) instruction - see Central Processor Unit (CPU). Take this into account when defining vector addresses. It is recommended that ALL vector addresses are defined.
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Memory Map
Advance Information 54 Memory Map
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Advance Information -- MC68HC08AZ60A
Section 3. RAM
3.1 Contents
3.2 3.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.2 Introduction
This section describes the 2048 bytes of random-access memory (RAM).
3.3 Functional Description
Addresses $0050 through $044F and $0A00 through $0DFF are RAM locations. The location of the stack RAM is programmable with the reset stack pointer instruction (RSP). The 16-bit stack pointer allows the stack RAM to be anywhere in the 64K-byte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM locations. Within page zero are 176 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access all page zero RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.
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RAM
NOTE:
For M68HC05, M6805, and M146805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
Advance Information 56 RAM
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Advance Information -- MC68HC08AZ60A
Section 4. ROM
4.1 Contents
4.2 4.3 4.4 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Introduction
This section describes the operation of the embedded ROM memory.
4.3 Functional Description
The user ROM consists of up to 61,744 bytes located in address ranges $0450--$04FF, $0580--$05FF and $0E00-$FDFF. The monitor ROM and vectors are located from $FE20-$FF5F. Fifty-two user vectors, $FFCC-$FFFF, are dedicated to user-defined reset and interrupt vectors.
4.4 Security
Security has been incorporated into the MC68HC08AZ60A to prevent external viewing of the ROM contents(1). This feature is selected by a mask option and ensures that customer-developed software remains proprietary. See Mask Options on page 167.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM difficult for unauthorized users.
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ROM
Advance Information 58 ROM
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Advance Information -- MC68HC08AZ60A
Section 5. EEPROM-1
5.1 Contents
5.2 5.3 5.4 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . 61
5.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 5.5.1 EEPROM-1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.5.2 EEPROM-1 Timebase Requirements . . . . . . . . . . . . . . . . 62 5.5.3 EEPROM-1 Program/Erase Protection . . . . . . . . . . . . . . . 63 5.5.4 EEPROM-1 Block Protection . . . . . . . . . . . . . . . . . . . . . . .64 5.5.5 EEPROM-1 Programming and Erasing. . . . . . . . . . . . . . . 64 5.6 EEPROM-1 Register Descriptions. . . . . . . . . . . . . . . . . . . . . 69 5.6.1 EEPROM-1 Control Register . . . . . . . . . . . . . . . . . . . . . . .69 5.6.2 EEPROM-1 Array Configuration Register . . . . . . . . . . . . 71 5.6.3 EEPROM-1 Nonvolatile Register. . . . . . . . . . . . . . . . . . . . 73 5.6.4 EEPROM-1 Timebase Divider Register . . . . . . . . . . . . . . 74 5.6.5 EEPROM-1 Timebase Divider Non-Volatile Register . . . 76 5.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2 Introduction
This section describes the 512 bytes of electrically erasable programmable read-only memory (EEPROM) residing at address range $0800 to $09FF. There are 1024 bytes of EEPROM available on the MC68HC08AZ60A which are physically located in two 512 byte arrays.
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EEPROM-1
For information relating to the array covering address range $0600 to $07FF please see EEPROM-2 on page 79.
5.3 Features
Features of the EEPROM-1 include the following: * * * * * * * 512 bytes Non-Volatile Memory Byte, Block, or Bulk Erasable Non-Volatile EEPROM-1 Configuration and Block Protection Options On-Chip Charge Pump for Programming/Erasing Program/Erase Protection Option Read Protection Option (in Monitor Mode) AUTO Bit Driven Programming/Erasing Time Feature
Advance Information 60 EEPROM-1
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 EEPROM-1 Register Summary
5.4 EEPROM-1 Register Summary
The EEPROM-1 Register Summary is shown in Figure 5-1.
Addr. Register Name Bit 7 6 R 5 R 4 R 3 R 2 EEDIV10 1 EEDIV9 Bit 0 EEDIV8
$FE10
Read: EE1DIV Non-volatile EEDIVSECD Register High Write: (EE1DIVHNVR)* Reset: Read: EE1DIV Non-volatile EEDIV7 Register Low Write: (EE1DIVLNVR)* Reset: Read: EE1 Divider Register High Write: (EE1DIVH) Reset: Read:
EEDIVSECD
Unaffected by reset; $FF when blank EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
$FE11
Unaffected by reset; $FF when blank 0 0 0 0 EEDIV10 Contents of EE1DIVHNVR ($FE10), Bits [6:3] = 0 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEDIV9 EEDIV8
$FE1A
$FE1B
EEDIV7 EE1 Divider Register Low Write: (EE1DIVL) Reset:
Contents of EE1DIVLNVR ($FE11) EEBP0
$FE1C
Read: EEPROM-1 Non-volatile UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEBP1 Register Write: (EE1NVR)* Reset: Unaffected by reset; $FF when blank; factory programmed $F0 Read: EEPROM-1 Control UNUSED Register Write: (EE1CR) Reset: 0 0 EEOFF 0 0 EERAS1 0 EERAS0 0 EELAT 0 AUTO 0 EEBP1
EEPGM 0 EEBP0
$FE1D
$FE1F
Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEPROM-1 Array Configuration Register Write: (EE1ACR) Reset: Contents of EE1NVR ($FE1C)
* Non-volatile EEPROM register; write by programming. = Unimplemented R = Reserved UNUSED = Unused
Figure 5-1. EEPROM-1 Register Summary
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Advance Information 61
EEPROM-1 5.5 Functional Description
The 512 bytes of EEPROM-1 are located at $0800-$09FF and can be programmed or erased without an additional external high voltage supply. The program and erase operations are enabled through the use of an internal charge pump. For each byte of EEPROM, the write/erase endurance is 10,000 cycles.
5.5.1 EEPROM-1 Configuration The 8-bit EEPROM-1 Non-Volatile Register (EE1NVR) and the 16-bit EEPROM-1 Timebase Divider Non-Volatile Register (EE1DIVNVR) contain the default settings for the following EEPROM-1 configurations: * * * EEPROM-1 Timebase Reference EEPROM-1 Program/Erase Protection EEPROM-1 Block Protection
EE1NVR and EE1DIVNVR are non-volatile EEPROM registers. They are programmed and erased in the same way as EEPROM bytes. The contents of these registers are loaded into their respective volatile registers during a MCU reset. The values in these read/write volatile registers define the EEPROM-1 configurations. For EE1NVR, the corresponding volatile register is the EEPROM-1 Array Configuration Register (EEACR). For the EE1DIVNVR (two 8-bit registers: EE1DIVHNVR and EE1DIVLNVR), the corresponding volatile register is the EEPROM-1 Divider Register (EE1DIV: EE1DIVH and EE1DIVL).
5.5.2 EEPROM-1 Timebase Requirements A 35s timebase is required by the EEPROM-1 control circuit for program and erase of EEPROM-1 content. This timebase is derived from dividing the CGMXCLK or bus clock (selected by EEDIVCLK bit in Mask Option Register B) using a timebase divider circuit controlled by the 16-bit EEPROM-1 Timebase Divider EE1DIV Register (EE1DIVH and EE1DIVL).
Advance Information 62 EEPROM-1 MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 Functional Description
As the CGMXCLK or bus clock is user selected, the EEPROM-1 Timebase Divider Register must be configured with the appropriate value to obtain the 35 s. The timebase divider value is calculated by using the following formula: EE1DIV= INT[Reference Frequency(Hz) x 35 x10-6 +0.5] This value is written to the EEPROM-1 Timebase Divider Register (EE1DIVH and EE1DIVL) or programmed into the EEPROM-1 Timebase Divider Non-Volatile Register prior to any EEPROM-1 program or erase operations(see EEPROM-1 Configuration on page 62 and EEPROM-1 Timebase Requirements on page 62).
5.5.3 EEPROM-1 Program/Erase Protection The EEPROM-1 has a special feature that designates the 16 bytes of addresses from $08F0 to $08FF to be permanently secured. This program/erase protect option is enabled by programming the EEPRTCT bit in the EEPROM-1 Non-Volatile Register (EE1NVR) to a logic zero. Once the EEPRTCT bit is programmed to 0 for the first time: * * * * * Programming and erasing of secured locations $08F0 to $08FF is permanently disabled. Secured locations $08F0 to $08FF can be read as normal. Programming and erasing of EE1NVR is permanently disabled. Bulk and Block Erase operations are disabled for the unprotected locations $0800-$08EF, $0900-$09FF. Single byte program and erase operations are still available for locations $0800-$08EF and $0900-$09FF for all bytes that are not protected by the EEPROM-1 Block Protect EEBPx bits (see EEPROM-1 Block Protection on page 64 and EEPROM-1 Array Configuration Register on page 71).
NOTE:
Once armed, the protect option is permanently enabled. As a consequence, all functions in the EE1NVR will remain in the state they were in immediately before the security was enabled.
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Advance Information 63
EEPROM-1
5.5.4 EEPROM-1 Block Protection The 512 bytes of EEPROM-1 are divided into four 128-byte blocks. Each of these blocks can be protected from erase/program operations by setting the EEBPx bit in the EE1NVR. Table 5-1 shows the address ranges for the blocks. Table 5-1. EEPROM-1 Array Address Blocks
Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 Address Range $0800-$087F $0880-$08FF $0900-$097F $0980-$09FF
These bits are effective after a reset or a upon read of the EE1NVR register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EE1NVR register and then reading the EE1NVR register. Please see EEPROM-1 Array Configuration Register on page 71 for more information.
NOTE:
Once EEDIVSECD in the EE1DIVHNVR is programmed to 0 and after a system reset, the EE1DIV security feature is permanently enabled because the EEDIVSECD bit in the EE1DIVH is always loaded with 0 thereafter. Once this security feature is armed, erase and program mode are disabled for EE1DIVHNVR and EE1DIVLNVR. Modifications to the EE1DIVH and EE1DIVL registers are also disabled. Therefore, be cautious on programming a value into the EE1DIVHNVR.
5.5.5 EEPROM-1 Programming and Erasing The unprogrammed or erase state of an EEPROM-1 bit is a logic 1. The factory default for all bytes within the EEPROM-1 array is $FF. The programming operation changes an EEPROM-1 bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a single programming operation, the minimum EEPROM-1 programming size is one bit; the maximum is eight bits (one byte).
Advance Information 64 EEPROM-1
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 Functional Description
The erase operation changes an EEPROM-1 bit from logic 0 to logic 1. In a single erase operation, the minimum EEPROM-1 erase size is one byte; the maximum is the entire EEPROM-1 array. The EEPROM-1 can be programmed such that one or multiple bits are programmed (written to a logic 0) at a time. However, the user may never program the same bit location more than once before erasing the entire byte. In other words, the user is not allowed to program a logic 0 to a bit that is already programmed (bit state is already logic 0). For some applications it might be advantageous to track more than 10K events with a single byte of EEPROM-1 by programming one bit at a time. For that purpose, a special selective bit programming technique is available. An example of this technique is illustrated in Table 5-2. Table 5-2. Example Selective Bit Programming Description
Description Original state of byte (erased) First event is recorded by programming bit position 0 Second event is recorded by programming bit position 1 Third event is recorded by programming bit position 2 Fourth event is recorded by programming bit position 3 Events five through eight are recorded in a similar fashion Program Data in Binary n/a 1111:1110 1111:1101 1111:1011 1111:0111 Result in Binary 1111:1111 1111:1110 1111:1100 1111:1000 1111:0000
Note that none of the bit locations are actually programmed more than once although the byte was programmed eight times. When this technique is utilized, a program/erase cycle is defined as multiple program sequences (up to eight) to a unique location followed by a single erase operation.
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EEPROM-1
5.5.5.1 Program/Erase Using AUTO Bit An additional feature available for EEPROM-1 program and erase operations is the AUTO mode. When enabled, AUTO mode will activate an internal timer that will automatically terminate the program/erase cycle and clear the EEPGM bit. Please see EEPROM-1 Programming on page 66, EEPROM-1 Erasing on page 67 and EEPROM-1 Control Register on page 69 for more information. 5.5.5.2 EEPROM-1 Programming The unprogrammed or erase state of an EEPROM-1 bit is a logic 1. Programming changes the state to a logic 0. Only EEPROM-1 bytes in the non-protected blocks and the EE1NVR register can be programmed. Use the following procedure to program a byte of EEPROM-1: 1. Clear EERAS1 and EERAS0 and set EELAT in the EE1CR.(A)
NOTE:
If using the AUTO mode, also set the AUTO bit during Step 1. 2. Write the desired data to the desired EEPROM-1 address.(B) 3. Set the EEPGM bit.(C) Go to Step 7 if AUTO is set. 4. Wait for time, tEEPGM, to program the byte. 5. Clear EEPGM bit. 6. Wait for time, tEEFPV, for the programming voltage to fall. Go to Step 8. 7. Poll the EEPGM bit until it is cleared by the internal timer.(D) 8. Clear EELAT bits.(E)
NOTE:
A. EERAS1 and EERAS0 must be cleared for programming. Setting the EELAT bit configures the address and data buses to latch data for programming the array. Only data with a valid EEPROM-1 address will be latched. If EELAT is set, other writes to the EE1CR will be allowed after a valid EEPROM-1 write. B. If more than one valid EEPROM-1 write occurs, the last address and data will be latched overriding the previous address and data. Once data
Advance Information 66 EEPROM-1
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 Functional Description
is written to the desired address, do not read EEPROM-1 locations other than the written location. (Reading an EEPROM-1 location returns the latched data and causes the read address to be latched). C. The EEPGM bit cannot be set if the EELAT bit is cleared or a nonvalid EEPROM-1 address is latched. This is to ensure proper programming sequence. Once EEPGM is set, do not read any EEPROM-1 locations; otherwise, the current program cycle will be unsuccessful. When EEPGM is set, the on-board programming sequence will be activated. D. The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEEPGM. However, on other MCUs, this delay time may be different. For forward compatibility, software should not make any dependency on this delay time. E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-1 array. 5.5.5.3 EEPROM-1 Erasing The programmed state of an EEPROM-1 bit is logic 0. Erasing changes the state to a logic 1. Only EEPROM-1 bytes in the non-protected blocks and the EE1NVR register can be erased. Use the following procedure to erase a byte, block or the entire EEPROM-1 array: 1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set EELAT in EE1CR.(A)
NOTE:
If using the AUTO mode, also set the AUTO bit in Step 1. 2. Byte erase: write any data to the desired address.(B) Block erase: write any data to an address within the desired block.(B) Bulk erase: write any data to an address within the array.(B) 3. Set the EEPGM bit.(C) Go to Step 7 if AUTO is set.
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Advance Information 67
EEPROM-1
4. Wait for a time: tEEBYTE for byte erase; tEEBLOCK for block erase; tEEBULK. for bulk erase. 5. Clear EEPGM bit. 6. Wait for a time, tEEFPV, for the erasing voltage to fall. Go to Step 8. 7. Poll the EEPGM bit until it is cleared by the internal timer.(D) 8. Clear EELAT bits.(E)
NOTE:
A. Setting the EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM-1 addresses will be latched. If EELAT is set, other writes to the EE1CR will be allowed after a valid EEPROM-1 write. B. If more than one valid EEPROM-1 write occurs, the last address and data will be latched overriding the previous address and data. Once data is written to the desired address, do not read EEPROM-1 locations other than the written location. (Reading an EEPROM-1 location returns the latched data and causes the read address to be latched). C. The EEPGM bit cannot be set if the EELAT bit is cleared or a nonvalid EEPROM-1 address is latched. This is to ensure proper programming sequence. Once EEPGM is set, do not read any EEPROM-1 locations; otherwise, the current program cycle will be unsuccessful. When EEPGM is set, the on-board programming sequence will be activated. D. The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEEBYTE /tEEBLOCK/tEEBULK. However, on other MCUs, this delay time may be different. For forward compatibility, software should not make any dependency on this delay time. E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-1 array.
Advance Information 68 EEPROM-1
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 EEPROM-1 Register Descriptions
5.6 EEPROM-1 Register Descriptions
Four I/O registers and three non-volatile registers control program, erase and options of the EEPROM-1 array.
5.6.1 EEPROM-1 Control Register This read/write register controls programming/erasing of the array.
Address: $FE1D Bit 7 Read: UNUSED Write: Reset: 0 0 0 = Unimplemented 0 0 0 0 0 6 0 EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM 5 4 3 2 1 Bit 0
Figure 5-2. EEPROM-1 Control Register (EE1CR) Bit 7-- Unused bit This read/write bit is software programmable but has no functionality. EEOFF -- EEPROM-1 Power Down This read/write bit disables the EEPROM-1 module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. 1 = Disable EEPROM-1 array 0 = Enable EEPROM-1 array
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Advance Information 69
EEPROM-1
EERAS1 and EERAS0 -- Erase/Program Mode Select Bits These read/write bits set the erase modes. Reset clears these bits. Table 5-3. EEPROM-1 Program/Erase Mode Select
EEBPx 0 0 0 0 1 X = don't care EERAS1 0 0 1 1 X EERAS0 0 1 0 1 X MODE Byte Program Byte Erase Block Erase Bulk Erase No Erase/Program
EELAT -- EEPROM-1 Latch Control This read/write bit latches the address and data buses for programming the EEPROM-1 array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. 1 = Buses configured for EEPROM-1 programming or erase operation 0 = Buses configured for normal operation AUTO -- Automatic Termination of Program/Erase Cycle When AUTO is set, EEPGM is cleared automatically after the program/erase cycle is terminated by the internal timer. (See note D for EEPROM-1 Programming on page 66, EEPROM-1 Erasing on page 67 and EEPROM Memory Characteristics on page 458) 1 = Automatic clear of EEPGM is enabled 0 = Automatic clear of EEPGM is disabled EEPGM -- EEPROM-1 Program/Erase Enable This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM-1 array if the EELAT bit is set and a write to a valid EEPROM-1 location has occurred. Reset clears the EEPGM bit. 1 = EEPROM-1 programming/erasing power switched on 0 = EEPROM-1 programming/erasing power switched off
Advance Information 70 EEPROM-1 MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 EEPROM-1 Register Descriptions
NOTE:
Writing logic 0s to both the EELAT and EEPGM bits with a single instruction will clear EEPGM only to allow time for the removal of high voltage.
5.6.2 EEPROM-1 Array Configuration Register The EEPROM-1 array configuration register configures EEPROM-1 security and EEPROM-1 block protection. This read-only register is loaded with the contents of the EEPROM-1 non-volatile register (EE1NVR) after a reset.
Address:
$FE1F Bit 7 6 5 4 3 EEBP3 2 EEBP2 1 EEBP1 Bit 0 EEBP0
Read: UNUSED UNUSED UNUSED EEPRTCT Write: Reset:
Contents of EE1NVR ($FE1C)
Figure 5-3. EEPROM-1 Array Configuration Register (EE1ACR) Bit 7:5 -- Unused Bits These read/write bits are software programmable but have no functionality. EEPRTCT -- EEPROM-1 Protection Bit The EEPRTCT bit is used to enable the security feature in the EEPROM-1 (see EEPROM-1 Program/Erase Protection on page 63). 1 = EEPROM-1 security disabled 0 = EEPROM-1 security enabled This feature is a write-once feature. Once the protection is enabled it may not be disabled.
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EEPROM-1
EEBP[3:0] -- EEPROM-1 Block Protection Bits These bits prevent blocks of EEPROM-1 array from being programmed or erased. 1 = EEPROM-1 array block is protected 0 = EEPROM-1 array block is unprotected
Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 Address Range $0800-$087F $0880-$08FF $0900-$097F $0980-$09FF
Table 5-4. EEPROM-1 Block Protect and Security Summary
Address Range EEBPx EEPRTCT = 1 Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected EEPRTCT = 0 Byte Programming Available Only Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected
EEBP0 = 0 $0800 - $087F EEBP0 = 1
EEBP1 = 0 $0880 - $08EF EEBP1 = 1
EEBP1 = 0 $08F0 - $08FF EEBP1 = 1
Secured (No Programming or Erasing)
EEBP2 = 0 $0900 - $097F EEBP2 = 1
Advance Information 72 EEPROM-1
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 EEPROM-1 Register Descriptions
Table 5-4. EEPROM-1 Block Protect and Security Summary
Address Range EEBPx EEPRTCT = 1 Byte Programming Available Bulk, Block and Byte Available Protected EEPRTCT = 0 Byte Programming Available Only Byte Erasing Available Protected
EEBP3 = 0 $0980 - $09FF EEBP3 = 1
5.6.3 EEPROM-1 Nonvolatile Register The contents of this register is loaded into the EEPROM-1 array configuration register (EE1ACR) after a reset. This register is erased and programmed in the same way as an EEPROM-1 byte. (See EEPROM-1 Control Register on page 69 for individual bit descriptions).
Address: $FE1C Bit 7 Read: UNUSED UNUSED UNUSED EEPRTCT Write: Reset: = Unimplemented PV PV = Programmed value or 1 in the erased state. EEBP3 EEBP2 EEBP1 EEBP0 6 5 4 3 2 1 Bit 0
Figure 5-4. EEPROM-1 Nonvolatile Register (EE1NVR)
NOTE:
The EE1NVR will leave the factory programmed with $F0 such that the full array is available and unprotected.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-1
Advance Information 73
EEPROM-1
5.6.4 EEPROM-1 Timebase Divider Register The 16-bit EEPROM-1 timebase divider register consists of two 8-bit registers: EE1DIVH and EE1DIVL. The 11-bit value in this register is used to configure the timebase divider circuit to obtain the 35 s timebase for EEPROM-1 control. These two read/write registers are respectively loaded with the contents of the EEPROM-1 timebase divider non-volatile registers (EE1DIVHNVR and EE1DIVLNVR) after a reset.
Address: $FE1A Bit 7 Read:
EEDIVSECD
6 0
5 0
4 0
3 0
2 EEDIV10
1 EEDIV9
Bit 0 EEDIV8
Write: Reset: Contents of EE1DIVHNVR ($FE10), Bits [6:3] = 0 = Unimplemented
Figure 5-5. EE1DIV Divider High Register (EE1DIVH)
Address:
$FE1B Bit 7 6 EEDIV6 5 EEDIV5 4 EEDIV4 3 EEDIV3 2 EEDIV2 1 EEDIV1 Bit 0 EEDIV0
Read: EEDIV7 Write: Reset: Contents of EE1DIVLNVR ($FE11)
Figure 5-6. EE1DIV Divider Low Register (EE1DIVL)
Advance Information 74 EEPROM-1
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 EEPROM-1 Register Descriptions
EEDIVSECD -- EEPROM-1 Divider Security Disable This bit enables/disables the security feature of the EE1DIV registers. When EE1DIV security feature is enabled, the state of the registers EE1DIVH and EE1DIVL are locked (including EEDIVSECD bit). The EE1DIVHNVR and EE1DIVLNVR non-volatile memory registers are also protected from being erased/programmed. 1 = EE1DIV security feature disabled 0 = EE1DIV security feature enabled EEDIV[10:0] -- EEPROM-1 Timebase Prescaler These prescaler bits store the value of EE1DIV which is used as the divisor to derive a timebase of 35s from the selected reference clock source (CGMXCLK or bus clock in the MORB register) for the EEPROM-1 related internal timer and circuits. EE1DIV[10:0] bits are readable at any time. They are writable when EELAT = 0 and EEDIVSECD = 1. The EE1DIV value is calculated by the following formula: EE1DIV= INT[Reference Frequency(Hz) x 35 x10-6 +0.5] Where the result inside the bracket is rounded down to the nearest integer value For example, if the reference frequency is 4.9152MHz, the EE1DIV value is 172
NOTE:
Programming/erasing the EEPROM-1 with an improper EE1DIV value may result in data lost and reduce endurance of the EEPROM-1 device.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-1
Advance Information 75
EEPROM-1
5.6.5 EEPROM-1 Timebase Divider Non-Volatile Register The 16-bit EEPROM-1 timebase divider non-volatile register consists of two 8-bit registers: EE1DIVHNVR and EE1DIVLNVR. The contents of these two registers are respectively loaded into the EEPROM-1 timebase divider registers, EE1DIVH and EE1DIVL, after a reset. These two registers are erased and programmed in the same way as an EEPROM-1 byte.
Address: $FE10 Bit 7 Read:
EEDIVSECD
6 R
5 R
4 R
3 R
2 EEDIV10
1 EEDIV9
Bit 0 EEDIV8
Write: Reset: R Unaffected by reset; $FF when blank = Reserved
Figure 5-7. EEPROM-1 Divider Non-Volatile Register High (EE1DIVHNVR))
Address:
$FE11 Bit 7 6 EEDIV6 5 EEDIV5 4 EEDIV4 3 EEDIV3 2 EEDIV2 1 EEDIV1 Bit 0 EEDIV0
Read: EEDIV7 Write: Reset: Unaffected by reset; $FF when blank
Figure 5-8. EEPROM-1 Divider Non-Volatile Register Low (EE1DIVLNVR) These two registers are protected from erase and program operations if the EEDIVSECD is set to logic 1 in the EE1DIVH (see EEPROM-1 Timebase Divider Register) or programmed to a logic 1 in the EE1DIVHNVR.
Advance Information 76 EEPROM-1
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-1 Low-Power Modes
NOTE:
Once EEDIVSECD in the EE1DIVHNVR is programmed to 0 and after a system reset, the EE1DIV security feature is permanently enabled because the EEDIVSECD bit in the EE1DIVH is always loaded with 0 thereafter. Once this security feature is armed, erase and program mode are disabled for EE1DIVHNVR and EE1DIVLNVR. Modifications to the EE1DIVH and EE1DIVL registers are also disabled. Therefore, care should be taken before programming a value into the EE1DIVHNVR.
5.7 Low-Power Modes
The WAIT and STOP instructions can put the MCU in low powerconsumption standby modes.
5.7.1 Wait Mode The WAIT instruction does not affect the EEPROM-1. It is possible to start the program or erase sequence on the EEPROM-1 and put the MCU in wait mode.
5.7.2 Stop Mode The STOP instruction reduces the EEPROM-1 power consumption to a minimum. The STOP instruction should not be executed while a programming or erasing sequence is in progress. If stop mode is entered while EELAT and EEPGM are set, the programming sequence will be stopped and the programming voltage to the EEPROM-1 array removed. The programming sequence will be restarted after leaving stop mode; access to the EEPROM-1 is only possible after the programming sequence has completed. If stop mode is entered while EELAT and EEPGM is cleared, the programming sequence will be terminated abruptly. In either case, the data integrity of the EEPROM-1 is not guaranteed.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-1
Advance Information 77
EEPROM-1
Advance Information 78 EEPROM-1
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 6. EEPROM-2
6.1 Contents
6.2 6.3 6.4 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 EEPROM-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . 81
6.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6.5.1 EEPROM-2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.5.2 EEPROM-2 Timebase Requirements . . . . . . . . . . . . . . . . 82 6.5.3 EEPROM-2 Program/Erase Protection . . . . . . . . . . . . . . . 83 6.5.4 EEPROM-2 Block Protection . . . . . . . . . . . . . . . . . . . . . . .84 6.5.5 EEPROM-2 Programming and Erasing. . . . . . . . . . . . . . . 84 6.6 EEPROM-2 Register Descriptions. . . . . . . . . . . . . . . . . . . . . 89 6.6.1 EEPROM-2 Control Register . . . . . . . . . . . . . . . . . . . . . . .89 6.6.2 EEPROM-2 Array Configuration Register . . . . . . . . . . . . 91 6.6.3 EEPROM-2 Nonvolatile Register. . . . . . . . . . . . . . . . . . . . 93 6.6.4 EEPROM-2 Timebase Divider Register . . . . . . . . . . . . . . 94 6.6.5 EEPROM-2 Timebase Divider Non-Volatile Register . . . 96 6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.2 Introduction
This section describes the 512 bytes of electrically erasable programmable read-only memory (EEPROM) residing at address range $0600 to $07FF. There are 1024 bytes of EEPROM available on the MC68HC08AZ60A which are physically located in two 512 byte arrays.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-2
Advance Information 79
EEPROM-2
For information relating to the array covering address range $0800 to $09FF please see EEPROM-1 on page 59.
6.3 Features
Features of the EEPROM-2 include the following: * * * * * * * 512 bytes Non-Volatile Memory Byte, Block, or Bulk Erasable Non-Volatile EEPROM-2 Configuration and Block Protection Options On-Chip Charge Pump for Programming/Erasing Program/Erase Protection Option Read Protection Option (in Monitor Mode) AUTO Bit Driven Programming/Erasing Time Feature
Advance Information 80 EEPROM-2
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-2 EEPROM-2 Register Summary
6.4 EEPROM-2 Register Summary
The EEPROM-2 Register Summary is shown in Figure 6-1.
Addr. Register Name Bit 7 6 R 5 R 4 R 3 R 2 EEDIV10 1 EEDIV9 Bit 0 EEDIV8
$FF70
Read: EE2DIV Non-volatile EEDIVSECD Register High Write: (EE2DIVHNVR)* Reset: Read: EE2DIV Non-volatile EEDIV7 Register Low Write: (EE2DIVLNVR)* Reset: Read: EE2 Divider Register High Write: (EE2DIVH) Reset: Read:
EEDIVSECD
Unaffected by reset; $FF when blank EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
$FF71
Unaffected by reset; $FF when blank 0 0 0 0 EEDIV10 Contents of EE2DIVHNVR ($FF70), Bits [6:3] = 0 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEDIV9 EEDIV8
$FF7A
$FF7B
EEDIV7 EE2 Divider Register Low Write: (EE2DIVL) Reset:
Contents of EE2DIVLNVR ($FF71) EEBP0
$FF7C
Read: EEPROM-2 Non-volatile UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEBP1 Register Write: (EE2NVR)* Reset: Unaffected by reset; $FF when blank; factory programmed $F0 Read: EEPROM-2 Control UNUSED Register Write: (EE2CR) Reset: 0 0 EEOFF 0 0 EERAS1 0 EERAS0 0 EELAT 0 AUTO 0 EEBP1
EEPGM 0 EEBP0
$FF7D
$FF7F
Read: UNUSED UNUSED UNUSED EEPRTCT EEBP3 EEBP2 EEPROM-2 Array Configuration Register Write: (EE2ACR) Reset: Contents of EE2NVR ($FF7C)
* Non-volatile EEPROM register; write by programming. = Unimplemented R = Reserved UNUSED = Unused
Figure 6-1. EEPROM-2 Register Summary
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-2
Advance Information 81
EEPROM-2 6.5 Functional Description
The 512 bytes of EEPROM-2 are located at $0600-$07FF and can be programmed or erased without an additional external high voltage supply. The program and erase operations are enabled through the use of an internal charge pump. For each byte of EEPROM, the write/erase endurance is 10,000 cycles.
6.5.1 EEPROM-2 Configuration The 8-bit EEPROM-2 Non-Volatile Register (EE2NVR) and the 16-bit EEPROM-2 Timebase Divider Non-Volatile Register (EE2DIVNVR) contain the default settings for the following EEPROM-2 configurations: * * * EEPROM-2 Timebase Reference EEPROM-2 Program/Erase Protection EEPROM-2 Block Protection
EE2NVR and EE2DIVNVR are non-volatile EEPROM registers. They are programmed and erased in the same way as EEPROM bytes. The contents of these registers are loaded into their respective volatile registers during a MCU reset. The values in these read/write volatile registers define the EEPROM-2 configurations. For EE2NVR, the corresponding volatile register is the EEPROM-2 Array Configuration Register (EEACR). For the EE2DIVNVR (two 8-bit registers: EE2DIVHNVR and EE2DIVLNVR), the corresponding volatile register is the EEPROM-2 Divider Register (EE2DIV: EE2DIVH and EE2DIVL).
6.5.2 EEPROM-2 Timebase Requirements A 35s timebase is required by the EEPROM-2 control circuit for program and erase of EEPROM-2 content. This timebase is derived from dividing the CGMXCLK or bus clock (selected by EEDIVCLK bit in Mask Option Register B) using a timebase divider circuit controlled by the 16-bit EEPROM-2 Timebase Divider EE2DIV Register (EE2DIVH and EE2DIVL).
Advance Information 82 EEPROM-2 MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-2 Functional Description
As the CGMXCLK or bus clock is user selected, the EEPROM-2 Timebase Divider Register must be configured with the appropriate value to obtain the 35 s. The timebase divider value is calculated by using the following formula: EE2DIV= INT[Reference Frequency(Hz) x 35 x10-6 +0.5] This value is written to the EEPROM-2 Timebase Divider Register (EE2DIVH and EE2DIVL) or programmed into the EEPROM-2 Timebase Divider Non-Volatile Register prior to any EEPROM-2 program or erase operations(see EEPROM-2 Configuration on page 82 and EEPROM-2 Timebase Requirements on page 82).
6.5.3 EEPROM-2 Program/Erase Protection The EEPROM-2 has a special feature that designates the 16 bytes of addresses from $06F0 to $06FF to be permanently secured. This program/erase protect option is enabled by programming the EEPRTCT bit in the EEPROM-2 Non-Volatile Register (EE2NVR) to a logic zero. Once the EEPRTCT bit is programmed to 0 for the first time: * * * * * Programming and erasing of secured locations $06F0 to $06FF is permanently disabled. Secured locations $06F0 to $06FF can be read as normal. Programming and erasing of EE2NVR is permanently disabled. Bulk and Block Erase operations are disabled for the unprotected locations $0600-$06EF, $0700-$07FF. Single byte program and erase operations are still available for locations $0600-$06EF and $0700-$07FF for all bytes that are not protected by the EEPROM-2 Block Protect EEBPx bits (see EEPROM-2 Block Protection on page 84 and EEPROM-2 Array Configuration Register on page 91).
NOTE:
Once armed, the protect option is permanently enabled. As a consequence, all functions in the EE2NVR will remain in the state they were in immediately before the security was enabled.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-2
Advance Information 83
EEPROM-2
6.5.4 EEPROM-2 Block Protection The 512 bytes of EEPROM-2 are divided into four 128-byte blocks. Each of these blocks can be protected from erase/program operations by setting the EEBPx bit in the EE2NVR. Table 6-1 shows the address ranges for the blocks. Table 6-1. EEPROM-2 Array Address Blocks
Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 Address Range $0600-$067F $0680-$06FF $0700-$077F $0780-$07FF
These bits are effective after a reset or a upon read of the EE2NVR register. The block protect configuration can be modified by erasing/programming the corresponding bits in the EE2NVR register and then reading the EE2NVR register. Please see EEPROM-2 Array Configuration Register on page 91 for more information.
NOTE:
Once EEDIVSECD in the EE2DIVHNVR is programmed to 0 and after a system reset, the EE2DIV security feature is permanently enabled because the EEDIVSECD bit in the EE2DIVH is always loaded with 0 thereafter. Once this security feature is armed, erase and program mode are disabled for EE2DIVHNVR and EE2DIVLNVR. Modifications to the EE2DIVH and EE2DIVL registers are also disabled. Therefore, be cautious on programming a value into the EE2DIVHNVR.
6.5.5 EEPROM-2 Programming and Erasing The unprogrammed or erase state of an EEPROM-2 bit is a logic 1. The factory default for all bytes within the EEPROM-2 array is $FF. The programming operation changes an EEPROM-2 bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). In a single programming operation, the minimum EEPROM-2 programming size is one bit; the maximum is eight bits (one byte).
Advance Information 84 EEPROM-2
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-2 Functional Description
The erase operation changes an EEPROM-2 bit from logic 0 to logic 1. In a single erase operation, the minimum EEPROM-2 erase size is one byte; the maximum is the entire EEPROM-2 array. The EEPROM-2 can be programmed such that one or multiple bits are programmed (written to a logic 0) at a time. However, the user may never program the same bit location more than once before erasing the entire byte. In other words, the user is not allowed to program a logic 0 to a bit that is already programmed (bit state is already logic 0). For some applications it might be advantageous to track more than 10K events with a single byte of EEPROM-2 by programming one bit at a time. For that purpose, a special selective bit programming technique is available. An example of this technique is illustrated in Table 6-2. Table 6-2. Example Selective Bit Programming Description
Description Original state of byte (erased) First event is recorded by programming bit position 0 Second event is recorded by programming bit position 1 Third event is recorded by programming bit position 2 Fourth event is recorded by programming bit position 3 Events five through eight are recorded in a similar fashion Program Data in Binary n/a 1111:1110 1111:1101 1111:1011 1111:0111 Result in Binary 1111:1111 1111:1110 1111:1100 1111:1000 1111:0000
Note that none of the bit locations are actually programmed more than once although the byte was programmed eight times. When this technique is utilized, a program/erase cycle is defined as multiple program sequences (up to eight) to a unique location followed by a single erase operation.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-2
Advance Information 85
EEPROM-2
6.5.5.1 Program/Erase Using AUTO Bit An additional feature available for EEPROM-2 program and erase operations is the AUTO mode. When enabled, AUTO mode will activate an internal timer that will automatically terminate the program/erase cycle and clear the EEPGM bit. Please see EEPROM-2 Programming on page 86, EEPROM-2 Erasing on page 87 and EEPROM-2 Control Register on page 89 for more information. 6.5.5.2 EEPROM-2 Programming The unprogrammed or erase state of an EEPROM-2 bit is a logic 1. Programming changes the state to a logic 0. Only EEPROM-2 bytes in the non-protected blocks and the EE2NVR register can be programmed. Use the following procedure to program a byte of EEPROM-2: 1. Clear EERAS1 and EERAS0 and set EELAT in the EE2CR.(A)
NOTE:
If using the AUTO mode, also set the AUTO bit during Step 1. 2. Write the desired data to the desired EEPROM-2 address.(B) 3. Set the EEPGM bit.(C) Go to Step 7 if AUTO is set. 4. Wait for time, tEEPGM, to program the byte. 5. Clear EEPGM bit. 6. Wait for time, tEEFPV, for the programming voltage to fall. Go to Step 8. 7. Poll the EEPGM bit until it is cleared by the internal timer.(D) 8. Clear EELAT bits.(E)
NOTE:
A. EERAS1 and EERAS0 must be cleared for programming. Setting the EELAT bit configures the address and data buses to latch data for programming the array. Only data with a valid EEPROM-2 address will be latched. If EELAT is set, other writes to the EE2CR will be allowed after a valid EEPROM-2 write. B. If more than one valid EEPROM-2 write occurs, the last address and data will be latched overriding the previous address and data. Once data
Advance Information 86 EEPROM-2
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-2 Functional Description
is written to the desired address, do not read EEPROM-2 locations other than the written location. (Reading an EEPROM-2 location returns the latched data and causes the read address to be latched). C. The EEPGM bit cannot be set if the EELAT bit is cleared or a nonvalid EEPROM-2 address is latched. This is to ensure proper programming sequence. Once EEPGM is set, do not read any EEPROM-2 locations; otherwise, the current program cycle will be unsuccessful. When EEPGM is set, the on-board programming sequence will be activated. D. The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEEPGM. However, on other MCUs, this delay time may be different. For forward compatibility, software should not make any dependency on this delay time. E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-2 array. 6.5.5.3 EEPROM-2 Erasing The programmed state of an EEPROM-2 bit is logic 0. Erasing changes the state to a logic 1. Only EEPROM-2 bytes in the non-protected blocks and the EE2NVR register can be erased. Use the following procedure to erase a byte, block or the entire EEPROM-2 array: 1. Configure EERAS1 and EERAS0 for byte, block or bulk erase; set EELAT in EE2CR.(A)
NOTE:
If using the AUTO mode, also set the AUTO bit in Step 1. 2. Byte erase: write any data to the desired address.(B) Block erase: write any data to an address within the desired block.(B) Bulk erase: write any data to an address within the array.(B) 3. Set the EEPGM bit.(C) Go to Step 7 if AUTO is set.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-2
Advance Information 87
EEPROM-2
4. Wait for a time: tEEBYTE for byte erase; tEEBLOCK for block erase; tEEBULK. for bulk erase. 5. Clear EEPGM bit. 6. Wait for a time, tEEFPV, for the erasing voltage to fall. Go to Step 8. 7. Poll the EEPGM bit until it is cleared by the internal timer.(D) 8. Clear EELAT bits.(E)
NOTE:
A. Setting the EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM-2 addresses will be latched. If EELAT is set, other writes to the EE2CR will be allowed after a valid EEPROM-2 write. B. If more than one valid EEPROM-2 write occurs, the last address and data will be latched overriding the previous address and data. Once data is written to the desired address, do not read EEPROM-2 locations other than the written location. (Reading an EEPROM-2 location returns the latched data and causes the read address to be latched). C. The EEPGM bit cannot be set if the EELAT bit is cleared or a nonvalid EEPROM-2 address is latched. This is to ensure proper programming sequence. Once EEPGM is set, do not read any EEPROM-2 locations; otherwise, the current program cycle will be unsuccessful. When EEPGM is set, the on-board programming sequence will be activated. D. The delay time for the EEPGM bit to be cleared in AUTO mode is less than tEEBYTE /tEEBLOCK/tEEBULK. However, on other MCUs, this delay time may be different. For forward compatibility, software should not make any dependency on this delay time. E. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM-2 array.
Advance Information 88 EEPROM-2
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-2 EEPROM-2 Register Descriptions
6.6 EEPROM-2 Register Descriptions
Four I/O registers and three non-volatile registers control program, erase and options of the EEPROM-2 array.
6.6.1 EEPROM-2 Control Register This read/write register controls programming/erasing of the array.
Address: $FF7D Bit 7 Read: UNUSED Write: Reset: 0 0 0 = Unimplemented 0 0 0 0 0 6 0 EEOFF EERAS1 EERAS0 EELAT AUTO EEPGM 5 4 3 2 1 Bit 0
Figure 6-2. EEPROM-2 Control Register (EE2CR) Bit 7-- Unused bit This read/write bit is software programmable but has no functionality. EEOFF -- EEPROM-2 Power Down This read/write bit disables the EEPROM-2 module for lower power consumption. Any attempts to access the array will give unpredictable results. Reset clears this bit. 1 = Disable EEPROM-2 array 0 = Enable EEPROM-2 array
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-2
Advance Information 89
EEPROM-2
EERAS1 and EERAS0 -- Erase/Program Mode Select Bits These read/write bits set the erase modes. Reset clears these bits. Table 6-3. EEPROM-2 Program/Erase Mode Select
EEBPx 0 0 0 0 1 X = don't care EERAS1 0 0 1 1 X EERAS0 0 1 0 1 X MODE Byte Program Byte Erase Block Erase Bulk Erase No Erase/Program
EELAT -- EEPROM-2 Latch Control This read/write bit latches the address and data buses for programming the EEPROM-2 array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. 1 = Buses configured for EEPROM-2 programming or erase operation 0 = Buses configured for normal operation AUTO -- Automatic Termination of Program/Erase Cycle When AUTO is set, EEPGM is cleared automatically after the program/erase cycle is terminated by the internal timer. (See note D for EEPROM-2 Programming on page 86, EEPROM-2 Erasing on page 87 and EEPROM Memory Characteristics on page 458) 1 = Automatic clear of EEPGM is enabled 0 = Automatic clear of EEPGM is disabled EEPGM -- EEPROM-2 Program/Erase Enable This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM-2 array if the EELAT bit is set and a write to a valid EEPROM-2 location has occurred. Reset clears the EEPGM bit. 1 = EEPROM-2 programming/erasing power switched on 0 = EEPROM-2 programming/erasing power switched off
Advance Information 90 EEPROM-2 MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-2 EEPROM-2 Register Descriptions
NOTE:
Writing logic 0s to both the EELAT and EEPGM bits with a single instruction will clear EEPGM only to allow time for the removal of high voltage.
6.6.2 EEPROM-2 Array Configuration Register The EEPROM-2 array configuration register configures EEPROM-2 security and EEPROM-2 block protection. This read-only register is loaded with the contents of the EEPROM-2 non-volatile register (EE2NVR) after a reset.
Address:
$FF7F Bit 7 6 5 4 3 EEBP3 2 EEBP2 1 EEBP1 Bit 0 EEBP0
Read: UNUSED UNUSED UNUSED EEPRTCT Write: Reset:
Contents of EE2NVR ($FF7C)
Figure 6-3. EEPROM-2 Array Configuration Register (EE2ACR) Bit 7:5 -- Unused Bits These read/write bits are software programmable but have no functionality. EEPRTCT -- EEPROM-2 Protection Bit The EEPRTCT bit is used to enable the security feature in the EEPROM-2 (see EEPROM-2 Program/Erase Protection on page 83). 1 = EEPROM-2 security disabled 0 = EEPROM-2 security enabled This feature is a write-once feature. Once the protection is enabled it may not be disabled.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-2
Advance Information 91
EEPROM-2
EEBP[3:0] -- EEPROM-2 Block Protection Bits These bits prevent blocks of EEPROM-2 array from being programmed or erased. 1 = EEPROM-2 array block is protected 0 = EEPROM-2 array block is unprotected
Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 Address Range $0600-$067F $0680-$06FF $0700-$077F $0780-$07FF
Table 6-4. EEPROM-2 Block Protect and Security Summary
Address Range EEBPx EEPRTCT = 1 Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Bulk, Block and Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected EEPRTCT = 0 Byte Programming Available Only Byte Erasing Available Protected Byte Programming Available Only Byte Erasing Available Protected
EEBP0 = 0 $0600 - $067F EEBP0 = 1
EEBP1 = 0 $0680 - $06EF EEBP1 = 1
EEBP1 = 0 $06F0 - $06FF EEBP1 = 1
Secured (No Programming or Erasing)
EEBP2 = 0 $0700 - $077F EEBP2 = 1
Advance Information 92 EEPROM-2
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
EEPROM-2 EEPROM-2 Register Descriptions
Table 6-4. EEPROM-2 Block Protect and Security Summary
Address Range EEBPx EEPRTCT = 1 Byte Programming Available Bulk, Block and Byte Available Protected EEPRTCT = 0 Byte Programming Available Only Byte Erasing Available Protected
EEBP3 = 0 $0780 - $07FF EEBP3 = 1
6.6.3 EEPROM-2 Nonvolatile Register The contents of this register is loaded into the EEPROM-2 array configuration register (EE2ACR) after a reset. This register is erased and programmed in the same way as an EEPROM-2 byte. (See EEPROM-2 Control Register on page 89 for individual bit descriptions).
Address: $FF7C Bit 7 Read: UNUSED UNUSED UNUSED EEPRTCT Write: Reset: = Unimplemented PV PV = Programmed value or 1 in the erased state. EEBP3 EEBP2 EEBP1 EEBP0 6 5 4 3 2 1 Bit 0
Figure 6-4. EEPROM-2 Nonvolatile Register (EE2NVR)
NOTE:
The EE2NVR will leave the factory programmed with $F0 such that the full array is available and unprotected.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA EEPROM-2
Advance Information 93
EEPROM-2
6.6.4 EEPROM-2 Timebase Divider Register The 16-bit EEPROM-2 timebase divider register consists of two 8-bit registers: EE2DIVH and EE2DIVL. The 11-bit value in this register is used to configure the timebase divider circuit to obtain the 35 s timebase for EEPROM-2 control. These two read/write registers are respectively loaded with the contents of the EEPROM-2 timebase divider non-volatile registers (EE2DIVHNVR and EE2DIVLNVR) after a reset.
Address: $FF7A Bit 7 Read:
EEDIVSECD
6 0
5 0
4 0
3 0
2 EEDIV10
1 EEDIV9
Bit 0 EEDIV8
Write: Reset: Contents of EE2DIVHNVR ($FF70), Bits [6:3] = 0 = Unimplemented
Figure 6-5. EE2DIV Divider High Register (EE2DIVH)
Address:
$FF7B Bit 7 6 EEDIV6 5 EEDIV5 4 EEDIV4 3 EEDIV3 2 EEDIV2 1 EEDIV1 Bit 0 EEDIV0
Read: EEDIV7 Write: Reset: Contents of EE2DIVLNVR ($FF71)
Figure 6-6. EE2DIV Divider Low Register (EE2DIVL)
Advance Information 94 EEPROM-2
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EEPROM-2 EEPROM-2 Register Descriptions
EEDIVSECD -- EEPROM-2 Divider Security Disable This bit enables/disables the security feature of the EE2DIV registers. When EE2DIV security feature is enabled, the state of the registers EE2DIVH and EE2DIVL are locked (including EEDIVSECD bit). The EE2DIVHNVR and EE2DIVLNVR non-volatile memory registers are also protected from being erased/programmed. 1 = EE2DIV security feature disabled 0 = EE2DIV security feature enabled EEDIV[10:0] -- EEPROM-2 Timebase Prescaler These prescaler bits store the value of EE2DIV which is used as the divisor to derive a timebase of 35s from the selected reference clock source (CGMXCLK or bus clock in the MORB register) for the EEPROM-2 related internal timer and circuits. EE2DIV[10:0] bits are readable at any time. They are writable when EELAT = 0 and EEDIVSECD = 1. The EE2DIV value is calculated by the following formula: EE2DIV= INT[Reference Frequency(Hz) x 35 x10-6 +0.5] Where the result inside the bracket is rounded down to the nearest integer value For example, if the reference frequency is 4.9152MHz, the EE2DIV value is 172
NOTE:
Programming/erasing the EEPROM-2 with an improper EE2DIV value may result in data lost and reduce endurance of the EEPROM-2 device.
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EEPROM-2
6.6.5 EEPROM-2 Timebase Divider Non-Volatile Register The 16-bit EEPROM-2 timebase divider non-volatile register consists of two 8-bit registers: EE2DIVHNVR and EE2DIVLNVR. The contents of these two registers are respectively loaded into the EEPROM-2 timebase divider registers, EE2DIVH and EE2DIVL, after a reset. These two registers are erased and programmed in the same way as an EEPROM-2 byte.
Address: $FF70 Bit 7 Read:
EEDIVSECD
6 R
5 R
4 R
3 R
2 EEDIV10
1 EEDIV9
Bit 0 EEDIV8
Write: Reset: R Unaffected by reset; $FF when blank = Reserved
Figure 6-7. EEPROM-2 Divider Non-Volatile Register High (EE2DIVHNVR))
Address:
$FF71 Bit 7 6 EEDIV6 5 EEDIV5 4 EEDIV4 3 EEDIV3 2 EEDIV2 1 EEDIV1 Bit 0 EEDIV0
Read: EEDIV7 Write: Reset: Unaffected by reset; $FF when blank
Figure 6-8. EEPROM-2 Divider Non-Volatile Register Low (EE2DIVLNVR) These two registers are protected from erase and program operations if the EEDIVSECD is set to logic 1 in the EE2DIVH (see EEPROM-2 Timebase Divider Register) or programmed to a logic 1 in the EE2DIVHNVR.
Advance Information 96 EEPROM-2
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EEPROM-2 Low-Power Modes
NOTE:
Once EEDIVSECD in the EE2DIVHNVR is programmed to 0 and after a system reset, the EE2DIV security feature is permanently enabled because the EEDIVSECD bit in the EE2DIVH is always loaded with 0 thereafter. Once this security feature is armed, erase and program mode are disabled for EE2DIVHNVR and EE2DIVLNVR. Modifications to the EE2DIVH and EE2DIVL registers are also disabled. Therefore, care should be taken before programming a value into the EE2DIVHNVR.
6.7 Low-Power Modes
The WAIT and STOP instructions can put the MCU in low powerconsumption standby modes.
6.7.1 Wait Mode The WAIT instruction does not affect the EEPROM-2. It is possible to start the program or erase sequence on the EEPROM-2 and put the MCU in wait mode.
6.7.2 Stop Mode The STOP instruction reduces the EEPROM-2 power consumption to a minimum. The STOP instruction should not be executed while a programming or erasing sequence is in progress. If stop mode is entered while EELAT and EEPGM are set, the programming sequence will be stopped and the programming voltage to the EEPROM-2 array removed. The programming sequence will be restarted after leaving stop mode; access to the EEPROM-2 is only possible after the programming sequence has completed. If stop mode is entered while EELAT and EEPGM is cleared, the programming sequence will be terminated abruptly. In either case, the data integrity of the EEPROM-2 is not guaranteed.
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Advance Information 97
EEPROM-2
Advance Information 98 EEPROM-2
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Advance Information -- MC68HC08AZ60A
Section 7. Central Processor Unit (CPU)
7.1 Contents
7.2 7.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.4 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.4.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.4.2 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 7.4.3 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.4.4 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.4.5 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . .103 7.5 7.6 7.7 7.8 7.9 Arithmetic/Logic Unit (ALU). . . . . . . . . . . . . . . . . . . . . . . . . 105 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 106 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.2 Introduction
This section describes the central processor unit (CPU8). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU)
Advance Information 99
Central Processor Unit (CPU) 7.3 Features
Features of the CPU include the following: * * * * * * * * * * Full upward, object-code compatibility with M68HC05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with X-register manipulation instructions 8.4MHz CPU internal bus frequency 64K byte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Low-power STOP and WAIT Modes
7.4 CPU registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 15 H 15 15 X
0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC)
7 0 V11HINZC
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers
Advance Information 100 Central Processor Unit (CPU) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Central Processor Unit (CPU) CPU registers
7.4.1 Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 Read: A Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 7-2. Accumulator (A) 7.4.2 Index Register (H:X) The 16-bit index register allows indexed addressing of a 64K byte memory space. H is the upper byte of the index register and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand.
Bit 15 Read: H:X Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
X = Indeterminate
Figure 7-3. Index Register (H:X) The index register can also be used as a temporary data storage location.
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Central Processor Unit (CPU)
7.4.3 Stack Pointer (SP) The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15 Read: SP Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 7-4. Stack Pointer (SP)
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point only to RAM locations.
7.4.4 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
Advance Information 102 Central Processor Unit (CPU)
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Central Processor Unit (CPU) CPU registers
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15 Read: PC Write: Reset: Loaded with vector from $FFFE and $FFFF Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 7-5. Program Counter (PC) 7.4.5 Condition Code Register (CCR) The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to `1'. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: CCR Write: Reset: X 1 1 X 1 X X X 6 5 4 3 2 1 Bit 0
V
1
1
H
I
N
Z
C
X = Indeterminate
Figure 7-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow
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Central Processor Unit (CPU)
H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ADD or ADC operation. The halfcarry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled
NOTE:
To maintain M6805 compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return from interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (CLI).
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Central Processor Unit (CPU) Arithmetic/Logic Unit (ALU)
N -- Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions - such as bit test and branch, shift, and rotate - also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
7.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about CPU architecture.
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Central Processor Unit (CPU) 7.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low--power consumption standby modes.
7.6.1 WAIT Mode The WAIT instruction: * clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from WAIT mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
7.6.2 STOP Mode The STOP instruction: * clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from STOP mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
After exiting STOP mode, the CPU clock begins running after the oscillator stabilization delay.
7.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. See Break Module. The program counter vectors to $FFFC-$FFFD ($FEFC-$FEFD in monitor mode). A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
Advance Information 106 Central Processor Unit (CPU)
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Central Processor Unit (CPU) Instruction Set Summary
7.8 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set. Table 7-1. Instruction Set Summary
Operand
ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff
Address Mode
Opcode
Source Form
Operation
Description
VHI NZC
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP
Add with Carry
A (A) + (M) + (C)
IMM DIR EXT - IX2 IX1 IX SP1 SP2
A9 B9 C9 D9 E9 F9 9E E9 9E D9 AB BB CB DB EB FB 9E EB 9E DB A7 AF A4 B4 C4 D4 E4 F4 9E E4 9E D4 38 48 58 68 78 9E 68 37 47 57 67 77 9E 67
ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP
Add without Carry
A (A) + (M)
IMM DIR EXT - IX2 IX1 IX SP1 SP2
AIS #opr AIX #opr
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM
AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP
Logical AND
A (A) & (M)
IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2
ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
DIR INH INH - - IX1 IX SP1 DIR INH - - INH IX1 IX SP1
Arithmetic Shift Right
b7 b0
C
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Advance Information 107
Cycles
2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5
Effect on CCR
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Continued)
Operand
rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr
Address Mode
Opcode
Source Form
BCC rel
Operation
Description
PC (PC) + 2 + rel ? (C) = 0
VHI NZC
Branch if Carry Bit Clear
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR - - - - - - (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL
24
BCLR n, opr
Clear Bit n in M
Mn 0
11 13 15 17 19 1B 1D 1F
BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0 PC (PC) + 2 + rel ? (Z) | (N V) = 0 PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9E E5 9E D5 93 25 23 91
BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP
Bit Test
(A) & (M)
IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2
BLE opr BLO rel BLS rel BLT opr
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands)
PC (PC) + 2 + rel ? (Z) | (N V) = 1 PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1
- - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL
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Cycles
3 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3
Effect on CCR
Central Processor Unit (CPU) Instruction Set Summary
Table 7-1. Instruction Set Summary (Continued)
Operand
rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd
Address Mode
Opcode
Source Form
BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Description
PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel
VHI NZC
Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
- - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ----- DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR - - - - - (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
2C 2B 2D 26 2A 20
BRCLR n,opr,rel
Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
01 03 05 07 09 0B 0D 0F
BRN rel
Branch Never
PC (PC) + 2
21
BRSET n,opr,rel
Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
00 02 04 06 08 0A 0C 0E
BSET n,opr
Set Bit n in M
Mn 1
10 12 14 16 18 1A 1C 1E
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Advance Information 109
Cycles
3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4
Effect on CCR
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Continued)
Operand
rr dd rr ii rr ii rr ff rr rr ff rr dd ff ff ii dd hh ll ee ff ff ff ee ff dd ff ff ii ii+1 dd ii dd hh ll ee ff ff ff ee ff
Address Mode
Opcode
Source Form
Operation
Description
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel
VHI NZC
Branch to Subroutine
BSR rel
- - - - - - REL
AD
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP
Compare and Branch if Equal
PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00
DIR IMM - - - - - - IMM IX1+ IX+ SP1
31 41 51 61 71 9E 61
Clear Carry Bit Clear Interrupt Mask
C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00
- - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1
98 9A 3F 4F 5F 8C 6F 7F 9E 6F A1 B1 C1 D1 E1 F1 9E E1 9E D1 33 43 53 63 73 9E 63 65 75 A3 B3 C3 D3 E3 F3 9E E3 9E D3
Clear
CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP
Compare A with M
(A) - (M)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2
COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr
Complement (One's Complement)
M A X M M M
(M) = $FF - (M) (A) = $FF - (M) (X) = $FF - (M) (M) = $FF - (M) (M) = $FF - (M) (M) = $FF - (M)
DIR INH INH 0 - - 1 IX1 IX SP1 IMM DIR
Compare H:X with M
(H:X) - (M:M + 1)
--
CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP
Compare X with M
(X) - (M)
IMM DIR EXT - - IX2 IX1 IX SP1 SP2
Advance Information 110 Central Processor Unit (CPU)
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Cycles
4 5 4 4 5 4 6 1 2 3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5
Effect on CCR
Central Processor Unit (CPU) Instruction Set Summary
Table 7-1. Instruction Set Summary (Continued)
Operand
dd rr rr rr ff rr rr ff rr dd ff ff ii dd hh ll ee ff ff ff ee ff dd ff ff dd hh ll ee ff ff dd hh ll ee ff ff
Address Mode
Opcode
Source Form
DAA DBNZ opr,rel DBNZA rel DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV
Operation
Description
VHI NZC
Decimal Adjust A (A)10 A (A) - 1 or M (M) - 1 or X (X) - 1 PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 4 + rel ? (result) 0 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder
U - - INH
72
Decrement and Branch if Not Zero
DIR INH - - - - - - INH IX1 IX SP1
3B 4B 5B 6B 7B 9E 6B 3A 4A 5A 6A 7A 9E 6A 52 A8 B8 C8 D8 E8 F8 9E E8 9E D8 3C 4C 5C 6C 7C 9E 6C BC CC DC EC FC
Decrement
DIR INH INH --- IX1 IX SP1 - - - - INH
Divide
EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP
Exclusive OR M with A
A (A M)
IMM DIR EXT IX2 0--- IX1 IX SP1 SP2
INC opr INCA INCX INC opr,X INC ,X INC opr,SP
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
DIR INH INH --- IX1 IX SP1
JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X
Jump
PC Jump Address
DIR EXT - - - - - - IX2 IX1 IX
JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
DIR EXT - - - - - - IX2 IX1 IX
BD CD DD ED FD
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU)
Advance Information 111
Cycles
2 5 3 3 5 4 6 4 1 1 4 3 5 7 2 3 4 4 3 2 4 5 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4
Effect on CCR
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Continued)
Operand
ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff dd dd dd ii dd dd dd ff ff
Address Mode
Opcode
Source Form
Operation
Description
VHI NZC
LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP
Load A from M
A (M)
IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2
A6 B6 C6 D6 E6 F6 9E E6 9E D6 45 55 AE BE CE DE EE FE 9E EE 9E DE 38 48 58 68 78 9E 68 34 44 54 64 74 9E 64 4E 5E 6E 7E 42 30 40 50 60 70 9E 60 9D 62
LDHX #opr LDHX opr
Load H:X from M
H:X (M:M + 1)
0 - - - IMM DIR
LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP
Load X from M
X (M)
IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2
LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP
Logical Shift Left (Same as ASL)
C b7 b0
0
DIR INH INH - - IX1 IX SP1 DIR INH INH --0 IX1 IX SP1
Logical Shift Right
0 b7 b0
C
MOV MOV MOV MOV MUL
opr,opr opr,X+ #opr,opr X+,opr
Move
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
DD 0 - - - DIX+ IMD IX+D - 0 - - - 0 INH DIR INH - - INH IX1 IX SP1 - - - - - - INH - - - - - - INH
Unsigned multiply
NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA
Negate (Two's Complement)
No Operation Nibble Swap A
Advance Information 112 Central Processor Unit (CPU)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Cycles
2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3
Effect on CCR
Central Processor Unit (CPU) Instruction Set Summary
Table 7-1. Instruction Set Summary (Continued)
Operand
ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff ii dd hh ll ee ff ff ff ee ff
Address Mode
Opcode
Source Form
Operation
Description
VHI NZC
ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP
Inclusive OR A and M
A (A) | (M)
IMM DIR EXT 0 - - - IX2 IX1 IX SP1 SP2
AA BA CA DA EA FA 9E EA 9E DA 87 8B 89 86 8A 88 39 49 59 69 79 9E 69 36 46 56 66 76 9E 66 9C
PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
- - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH -- IX1 IX SP1 DIR INH INH - - IX1 IX SP1 - - - - - - INH
Rotate Left through Carry
C b7 b0
Rotate Right through Carry
b7 b0
C
Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
RTI
Return from Interrupt
INH
80
RTS
Return from Subroutine
- - - - - - INH
81 A2 B2 C2 D2 E2 F2 9E E2 9E D2 99
SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP
Subtract with Carry
A (A) - (M) - (C)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2
SEC
Set Carry Bit
C1
- - - - - 1 INH
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU)
Advance Information 113
Cycles
2 3 4 4 3 2 4 5 2 2 2 2 2 2 4 1 1 4 3 5 4 1 1 4 3 5 1 7 4 2 3 4 4 3 2 4 5 1
Effect on CCR
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Continued)
Operand
dd hh ll ee ff ff ff ee ff dd dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd ff ff
Address Mode
Opcode
Source Form
SEI
Operation
Description
I1
VHI NZC
Set Interrupt Mask
- - 1 - - - INH
9B B7 C7 D7 E7 F7 9E E7 9E D7 35 8E BF CF DF EF FF 9E EF 9E DF A0 B0 C0 D0 E0 F0 9E E0 9E D0
STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP
Store A in M
M (A)
DIR EXT IX2 0 - - - IX1 IX SP1 SP2
STHX opr STOP
Store H:X in M Enable IRQ Pin; Stop Oscillator
(M:M + 1) (H:X) I 0; Stop Oscillator
0 - - - DIR - - 0 - - - INH
STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP
Store X in M
M (X)
DIR EXT IX2 0 - - - IX1 IX SP1 SP2
SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Subtract
A (A) - (M)
IMM DIR EXT IX2 - - IX1 IX SP1 SP2
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
- - 1 - - - INH
83
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH INH 0--- IX1 IX SP1 - - - - - - INH
84 97 85 3D 4D 5D 6D 7D 9E 6D 95
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
Transfer SP to H:X
H:X (SP) + 1
Advance Information 114 Central Processor Unit (CPU)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Cycles
2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 9 2 1 1 3 1 1 3 2 4 2
Effect on CCR
Central Processor Unit (CPU) Opcode Map
1
Table 7-1. Instruction Set Summary (Continued)
Operand Address Mode Opcode Cycles
1 2
Source Form
TXA TXS
Operation
Description
A (X) (SP) (H:X) - 1
Effect on CCR VHI NZC
Transfer X to A Transfer H:X to SP
- - - - - - INH - - - - - - INH
9F 94
A Accumulatorn C Carry/borrow bitopr CCRCondition code registerPC ddDirect address of operandPCH dd rrDirect address of operand and relative offset of branch instructionPCL DDDirect to direct addressing modeREL DIRDirect addressing moderel DIX+Direct to indexed with post increment addressing moderr ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1 EXTExtended addressing modeSP2 ff Offset byte in indexed, 8-bit offset addressingSP H Half-carry bitU H Index register high byteV hh llHigh and low bytes of operand address in extended addressingX I Interrupt maskZ ii Immediate operand byte& IMDImmediate source to direct destination addressing mode| IMMImmediate addressing mode INHInherent addressing mode( ) IXIndexed, no offset addressing mode-( ) IX+Indexed, no offset, post increment addressing mode# IX+DIndexed with post increment to direct addressing mode IX1Indexed, 8-bit offset addressing mode IX1+Indexed, 8-bit offset, post increment addressing mode? IX2Indexed, 16-bit offset addressing mode: MMemory location N Negative bit--
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
7.9 Opcode Map
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Central Processor Unit (CPU)
Advance Information 115
116 Central Processor Unit (CPU) MOTOROLA
Advance Information MC68HC08AZ60A -- Rev 0.0
Central Processor Unit (CPU)
Bit Manipulation DIR DIR
MSB LSB
Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL
DIR 3
INH 4
Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1
SP1 9E6
IX 7
Control INH INH 8 9
IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM
DIR B
EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT 0
Register/Memory IX2 SP2 D 4 SUB IX2 4 CMP IX2 4 SBC IX2 4 CPX IX2 4 AND IX2 4 BIT IX2 4 LDA IX2 4 STA IX2 4 EOR IX2 4 ADC IX2 4 ORA IX2 4 ADD IX2 4 JMP IX2 6 JSR IX2 4 LDX IX2 4 STX IX2 9ED 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2
IX1 E
SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1
IX F
0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR
1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
0 1 2 3 4 5 6 7 8 9 A B C D E F INH IMM DIR EXT DD IX+D
4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
MSB LSB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Table 7-2. Opcode Map
Advance Information -- MC68HC08AZ60A
Section 8. System Integration Module (SIM)
8.1 Contents
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . 120 8.3.1 BusTiming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.3.2 Clock Start-Up From POR or LVI Reset . . . . . . . . . . . . . 121 8.3.3 Clocks in STOP and WAIT Mode. . . . . . . . . . . . . . . . . . . 121 8.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . .121 8.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.4.2 Active Resets From Internal Sources. . . . . . . . . . . . . . .123 8.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . .125 8.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . .125 8.4.2.4 Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . 126 8.5 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.5.1 SIM Counter During Power-On Reset. . . . . . . . . . . . . . .126 8.5.2 SIM Counter During STOP Mode Recovery . . . . . . . . . . 127 8.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . 127 8.6 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.6.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.6.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.7 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.7.1 Status Flag Protection in Break Mode . . . . . . . . . . . . . . 130 8.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.8.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.8.2 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
MC68HC08AZ60A -- Rev 0.0 MOTOROLA System Integration Module (SIM)
Advance Information 117
System Integration Module (SIM)
8.9 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.9.1 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . 134 8.9.2 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . 136 8.9.3 SIM Break Flag Control Register (SBFCR). . . . . . . . . . . 137
8.2 Introduction
This section describes the system integration module, which supports up to 24 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 8-1. Table 8-1 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals - STOP/WAIT/reset/break entry and recovery - Internal clock control * * Master reset control, including power-on reset (POR) and COP timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * CPU enable/disable timing
Advance Information 118 System Integration Module (SIM)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
System Integration Module (SIM) Introduction
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) SIM COUNTER COP CLOCK
CGMXCLK (FROM CGM) CGMOUT (FROM CGM)
/2
CLOCK CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
RESET PIN LOGIC
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 8-1. SIM Block Diagram Table 8-1. SIM I/O Register Summary
Register Name SIM Break Status Register (SBSR) R: W: Bit 7 R 6 R PIN 5 R COP 4 R ILOP 3 R ILAD 2 R 0 1 BW 0 LVI Bit 0 R 0 Addr. $FE00
SIM Reset Status Register (SRSR) SIM Break Flag Control Register (SBFCR)
R: POR W: BCFE R
$FE01 $FE03
R
R
R
R
R
R
R
= Reserved for factory test
= Unimplemented
MC68HC08AZ60A -- Rev 0.0 MOTOROLA System Integration Module (SIM)
Advance Information 119
System Integration Module (SIM)
Table 8-2 shows the internal signal names used in this section. Table 8-2. Signal Naming Conventions
Signal Name CGMXCLK CGMVCLK CGMOUT IAB IDB PORRST IRST R/W Description Buffered Version of OSC1 from Clock Generator Module (CGM) PLL Output PLL-based or OSC1-based clock output from CGM Module (Bus Clock = CGMOUT divided by two) Internal Address Bus Internal Data Bus Signal from the Power-on Reset Module to the SIM Internal Reset Signal Read/WriteSignal
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 8-2. This clock can come from either an external oscillator or from the on-chip PLL. See Clock Generator Module (CGM).
OSC1 CLOCK SELECT CIRCUIT
CGMXCLK
SIM COUNTER
CGMVCLK
/2
A B S*
CGMOUT
/2
BUS CLOCK GENERATORS
*When S = 1,
CGMOUT = B PLL BCS PTC3 MONITOR MODE USER MODE
SIM
CGM
Figure 8-2. CGM Clock Signals
Advance Information 120 System Integration Module (SIM) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
System Integration Module (SIM) Reset and System Initialization
8.3.1 BusTiming In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. See Clock Generator Module (CGM).
8.3.2 Clock Start-Up From POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has been completed. The RST pin is driven low by the SIM during this entire period. The bus clocks start upon completion of the timeout.
8.3.3 Clocks in STOP and WAIT Mode Upon exit from STOP mode (by an interrupt, break, or reset), the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the STOP delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. See STOP mode. In WAIT mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the WAIT mode subsection of each module to see if the module is active or inactive in WAIT mode. Some modules can be programmed to be active in WAIT mode.
8.4 Reset and System Initialization
The MCU has the following reset sources: * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA System Integration Module (SIM)
Advance Information 121
System Integration Module (SIM)
* * Illegal opcode Illegal address
All of these resets produce the vector $FFFE-FFFF ($FEFE-FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter, see SIM Counter on page 126, but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See SIM Registers.
8.4.1 External Pin Reset Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 8-3 for details. Figure 8-3 shows the relative timing. Table 8-3. PIN Bit Set Timing
Reset type POR/LVI All others Number of cycles required to set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
CGMOUT
RST
IAB
PC
VECT H
VECT L
Figure 8-3. External Reset Timing
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MC68HC08AZ60A -- Rev 0.0 MOTOROLA
System Integration Module (SIM) Reset and System Initialization
8.4.2 Active Resets From Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow for resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. See Figure 8-4. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 8-5. Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles, during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST as shown in Figure 8-4.
IRST RST PULLED LOW BY MCU 32 CYCLES CGMXCLK 32 CYCLES
RST
IAB
VECTOR HIGH
Figure 8-4. Internal Reset Timing The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET
Figure 8-5. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA System Integration Module (SIM)
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System Integration Module (SIM)
8.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: * * * * * * A POR pulse is generated The internal reset signal is asserted The SIM enables CGMOUT Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow the oscillator to stabilize The RST pin is driven low during the oscillator stabilization time The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared
OSC1
PORRST 4096 CYCLES CGMXCLK 32 CYCLES 32 CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 8-6. POR Recovery
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MC68HC08AZ60A -- Rev 0.0 MOTOROLA
System Integration Module (SIM) Reset and System Initialization
8.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, a value (any value) should be written to location $FFFF. Writing to location $FFFF clears the COP counter and bits 12 through 4 of the SIM counter. The SIM counter output, which occurs at least every 213 - 24 CGMXCLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ pin is held at VDD + VHI while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VDD + VHI on the RST pin disables the COP module. 8.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the STOP enable bit, STOP, in the mask option register is logic `0', the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 8.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
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System Integration Module (SIM)
NOTE:
Extra care should be exercised if code in this part has been taken from another HC08 with a different memory map since some legal addresses could become illegal addresses on a smaller ROM. It is the user's responsibility to check their code for illegal addresses. Older HC08s may have a different illegal address reset specification.
8.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. 64 CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources.
8.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in STOP mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly (COP) module. The SIM counter overflow supplies the clock for the COP module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
8.5.1 SIM Counter During Power-On Reset The power-on reset (POR) module detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine.
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MC68HC08AZ60A -- Rev 0.0 MOTOROLA
System Integration Module (SIM) Exception Control
8.5.2 SIM Counter During STOP Mode Recovery The SIM counter is also used for STOP mode recovery. The STOP instruction clears the SIM counter. After an interrupt or reset, the SIM senses the state of the short STOP recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic `1', then the STOP recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from STOP mode. External crystal applications should use the full STOP recovery time, that is, with SSREC cleared.
8.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See STOP mode for details). The SIM counter is free-running after all reset states, see Active Resets From Internal Sources on page 123 for counter control and internal reset recovery sequences.
8.6 Exception Control
Normal, sequential program execution can be changed in three different ways: * Interrupts - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * * Reset Break interrupts
8.6.1 Interrupts At the beginning of an interrupt, the CPU saves the CPU register contents onto the stack and sets the interrupt mask (I-bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal
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System Integration Module (SIM)
processing can resume. Figure 8-7 shows interrupt entry timing, and Figure 8-8 shows interrupt recovery timing.
.
MODULE INTERRUPT
I-bit
IAB
DUMMY
SP
SP - 1 PC - 1[7:0]
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDRESS
IDB
DUMMY
PC-1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 8-7. Interrupt Entry Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt may take precedence, regardless of priority, until the latched interrupt is serviced (or the I-bit is cleared). See Figure 8-8.
MODULE INTERRUPT I-BIT
IAB
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
IDB
CCR
A
X
PC - 1[7:0]
PC-1[15:8]
OPCODE
OPERAND
R/W
Figure 8-8. Interrupt Recovery
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System Integration Module (SIM) Exception Control
8.6.1.1 Hardware Interrupts Processing of a hardware interrupt begins after completion of the current instruction. When the instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I-bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 8-8 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 8-9. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine
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System Integration Module (SIM)
modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. 8.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I-bit) in the condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does.
8.6.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated.
8.7 Break Interrupts
The break module can stop normal program flow at a softwareprogrammable break point by asserting its break interrupt output. See Break Module. The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
8.7.1 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited.
Advance Information 130 System Integration Module (SIM) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
System Integration Module (SIM) Low-Power Modes
Status flags with a two-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
8.8 Low-Power Modes
Executing the STOP/WAIT instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
8.8.1 WAIT Mode In WAIT mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 8-10 shows the timing for WAIT mode entry. A module that is active during WAIT mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In WAIT mode, the CPU clocks are inactive. Refer to the WAIT mode subsection of each module to see if the module is active or inactive in WAIT mode. Some modules can be programmed to be active in WAIT mode. WAIT mode can also be exited by a reset or break. A break interrupt during WAIT mode sets the SIM break WAIT bit, BW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is `0', then the computer operating properly (COP) module is enabled and remains active in WAIT mode.
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System Integration Module (SIM)
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 8-10. WAIT Mode Entry Timing Figure 8-10 and Figure 8-12 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 8-11. WAIT Recovery From Interrupt or Break
32 Cycles IAB $6E0B
32 Cycles RST VCT H RST VCT L
IDB
$A6
$A6
$A6
RST
CGMXCLK
Figure 8-12. WAIT Recovery From Internal Reset
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System Integration Module (SIM) Low-Power Modes
8.8.2 STOP mode In STOP mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from STOP mode. Stacking for interrupts begins after the selected STOP recovery time has elapsed. Reset also causes an exit from STOP mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in STOP mode, stopping the CPU and peripherals. STOP recovery time is selectable using the SSREC bit in the mask option register (MOR). If SSREC is set, STOP recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from STOP mode.
NOTE:
External crystal applications should use the full STOP recovery time by clearing the SSREC bit. The break module is inactive in STOP mode. The STOP instruction does not affect break module register states. The SIM counter is held in reset from the execution of the STOP instruction until the beginning of STOP recovery. It is then used to time the recovery period. Figure 8-13 shows STOP mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 8-13. STOP Mode Entry Timing
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System Integration Module (SIM)
STOP RECOVERY PERIOD CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 8-14. STOP Mode Recovery From Interrupt
8.9 SIM Registers
The SIM has three memory mapped registers. Table 8-4 shows the mapping of these registers. Table 8-4. SIM Registers
Address $FE00 $FE01 $FE03 Register SBSR SRSR SBFCR Access mode User User User
8.9.1 SIM Break Status Register (SBSR) The SIM break status register contains a flag to indicate that a break caused an exit from STOP or WAIT mode.
Bit 7 SBSR $FE00 Read: 6 5 4 3 2 1 Bit 0
BW R R R R R R Note(1) 0
R = Reserved for factory test 1. Writing a logic `0' clears BW.
R
Write: Reset:
Figure 8-15. SIM Break Status Register (SBSR)
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MC68HC08AZ60A -- Rev 0.0 MOTOROLA
System Integration Module (SIM) SIM Registers
BW -- SIM Break WAIT This status bit is useful in applications requiring a return to WAIT mode after exiting from a break interrupt. BW can be cleared by writing a logic `0' to it. Reset clears BW. 1 = WAIT mode was exited by break interrupt 0 = WAIT mode was not exited by break interrupt BW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this.
; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE LOBYTE ; EQU EQU 5 6
If not BW, do RTI BRCLR TST BNE DEC DOLO RETURN DEC PULH RTI BW,SBSR, RETURN LOBYTE,SP DOLO HIBYTE,SP LOBYTE,SP ; See if WAIT mode was exited by break. ; ; If RETURNLO is not `0', ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT opcode. ; Restore H register.
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System Integration Module (SIM)
8.9.2 SIM Reset Status Register (SRSR) This register contains six flags that show the source of the last reset. The SIM reset status register can be cleared by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Bit 7 SRSR $FE01 Read: Write: POR: 1
6
5
4
3
2
1
Bit 0
POR
PIN
COP
ILOP
ILAD
0
LVI
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-16. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR
Advance Information 136 System Integration Module (SIM)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
System Integration Module (SIM) SIM Registers
8.9.3 SIM Break Flag Control Register (SBFCR) The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Bit 7 SBFCR $FE03 Read: 6 5 4 3 2 1 Bit 0
BCFE
Write: Reset: 0
R
R
R
R
R
R
R
R
= Reserved for factory test
Figure 8-17. SIM Break Flag Control Register (SBFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
MC68HC08AZ60A -- Rev 0.0 MOTOROLA System Integration Module (SIM)
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System Integration Module (SIM)
Advance Information 138 System Integration Module (SIM)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 9. Clock Generator Module (CGM)
9.1 Contents
9.2 9.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
9.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 9.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.4.2 Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . . 143 9.4.2.1 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . 145 9.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . . 145 9.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . . 149 9.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . 149 9.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . 150 9.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.5.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . 151 9.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . 151 9.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . .151 9.5.4 Analog Power Pin (VDDA). . . . . . . . . . . . . . . . . . . . . . . . . 152 9.5.5 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . 152 9.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . 152 9.5.7 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . 152 9.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . 152 9.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . 155 9.6.3 PLL Programming Register. . . . . . . . . . . . . . . . . . . . . . . 157 9.7 9.8
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM)
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
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Clock Generator Module (CGM)
9.8.1 9.8.2 9.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 160
9.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . 160 9.10.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . 160 9.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . . 162 9.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . 163 9.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . 163
9.2 Introduction
The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system clocks are derived. CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency generator designed for use with 1-MHz to 16-MHz crystals or ceramic resonators. The PLL can generate an 8-MHz bus frequency without using high frequency crystals.
9.3 Features
Features of the CGM include: * * * * * Phase-Locked Loop with Output Frequency in Integer Multiples of the Crystal Reference Programmable Hardware Voltage-Controlled Oscillator (VCO) for Low-Jitter Operation Automatic Bandwidth Control Mode for Low-Jitter Operation Automatic Frequency Lock Detector CPU Interrupt on Entry or Exit from Locked Condition
Advance Information 140 Clock Generator Module (CGM)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Clock Generator Module (CGM) Functional Description
9.4 Functional Description
The CGM consists of three major submodules: * * * Crystal oscillator circuit -- The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK. Phase-locked loop (PLL) -- The PLL generates the programmable VCO frequency clock CGMVCLK. Base clock selector circuit -- This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks are derived from CGMOUT.
Figure 9-1 shows the structure of the CGM.
9.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal enables the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock. CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM)
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Clock Generator Module (CGM)
OSC1 CLOCK SELECT CIRCUIT CGMRDV CGMRCLK BCS A
CGMXCLK
/2
CGMOUT B S* *When S = 1, CGMOUT = B
PTC3 VDDA CGMXFC VSS VRS7-VRS4 MONITOR MODE USER MODE PHASE DETECTOR LOOP FILTER PLL ANALOG VOLTAGE CONTROLLED OSCILLATOR
LOCK DETECTOR
BANDWIDTH CONTROL
INTERRUPT CONTROL
CGMINT
LOCK
AUTO
ACQ
PLLIE
PLLF
MUL7-MUL4
CGMVDV
FREQUENCY DIVIDER
CGMVCLK
Figure 9-1. CGM Block Diagram
Advance Information 142 Clock Generator Module (CGM)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Clock Generator Module (CGM) Functional Description
Register Name Read: PLL Control Register (PCTL) Write: Reset: Read: PLL Bandwidth Control Register Write: (PBWC) Reset: Read: PLL Programming Register (PPG) Write: Reset:
Bit 7 PLLIE 0
6 PLLF
5 PLLON 1
4 BCS 0
3 1
2 1
1 1
Bit 0 1
0 LOCK
1 0
1 0
1 0
1 0
AUTO 0
ACQ 0
XLD 0
0
0
0
0
0
MUL7 0
MUL6 1
MUL5 1
MUL4 0
VRS7 0
VRS6 1
VRS5 1
VRS4 0
= Unimplemented
Figure 9-2. I/O Register Summary Table 9-1. I/O Register Address Summary
Register Address PCTL $001C PBWC $001D PPG $001E
9.4.2 Phase-Locked Loop Circuit (PLL) The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 9.4.2.1 Circuits The PLL consists of these circuits: * * * * *
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Clock Generator Module (CGM)
Voltage-controlled oscillator (VCO) Modulo VCO frequency divider Phase detector Loop filter Lock detector
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Clock Generator Module (CGM)
The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fCGMVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fCGMVRS is equal to the nominal center-ofrange frequency, fNOM, (4.9152 MHz) times a linear factor L or (L)fNOM. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, fCGMRCLK, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV, running at a frequency fCGMRDV = fCGMRCLK. The VCO's output clock, CGMVCLK, running at a frequency fCGMVCLK, is fed back through a programmable modulo divider. The modulo divider reduces the VCO clock by a factor, N. The divider's output is the VCO feedback clock, CGMVDV, running at a frequency fCGMVDV = fCGMVCLK/N. See Programming the PLL for more information. The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the dc voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in Acquisition and Tracking Modes on page 145. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, fCGMRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison.
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9.4.2.2 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: * Acquisition mode -- In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. See PLL Bandwidth Control Register on page 155. Tracking mode -- In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. See Base Clock Selector Circuit on page 149. The PLL is automatically in tracking mode when it's not in acquisition mode or when the ACQ bit is set.
*
9.4.2.3 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See PLL Bandwidth Control Register on page 155. If PLL CPU interrupt requests are enabled, the software can wait for a PLL CPU interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. See Base Clock Selector Circuit on page 149. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. See Interrupts on page 159.
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These conditions apply when the PLL is in automatic bandwidth control mode: * The ACQ bit (See 9.6.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of the filter. See Acquisition and Tracking Modes on page 145. The ACQ bit is set when the VCO frequency is within a certain tolerance, trk, and is cleared when the VCO frequency is out of a certain tolerance, unt. See Electrical Specifications on page 445. The LOCK bit is a read-only indicator of the locked state of the PLL. The LOCK bit is set when the VCO frequency is within a certain tolerance, Lock, and is cleared when the VCO frequency is out of a certain tolerance, unl. See Electrical Specifications on page 445. CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's lock condition changes, toggling the LOCK bit. See PLL Control Register on page 153.
*
* *
*
The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fbusmax and require fast startup. The following conditions apply when in manual mode: * ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. Before entering tracking mode (ACQ = 1), software must wait a given time, tacq (see Electrical Specifications on page 445), after turning on the PLL by setting PLLON in the PLL control register (PCTL). Software must wait a given time, tal, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). The LOCK bit is disabled. CPU interrupts from the CGM are disabled.
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*
*
* *
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Clock Generator Module (CGM) Functional Description
9.4.2.4 Programming the PLL Use this 9-step procedure to program the PLL. The table below lists the variables used and their meaning (Please also reference Figure 9-1). Table 9-2. Variable Definitions
Variable Definition Desired Bus Clock Frequency Desired VCO Clock Frequency Chosen Reference Crystal Frequency Calculated VCO Clock Frequency Calculated Bus Clock Frequency Nominal VCO Center Frequency Shifted VCO Center Frequency
fBUSDES fVCLKDES fCGMRCLK fCGMVCLK fBUS fNOM fCGMVRS
1. Choose the desired bus frequency, fBUSDES. Example: fBUSDES = 8 MHz 2. Calculate the desired VCO frequency, fVCLKDES. fVCLKDES = 4 x fBUSDES Example: fVCLKDES = 4 x 8 MHz = 32 MHz 3. Using a reference frequency, fRCLK, equal to the crystal frequency, calculate the VCO frequency multiplier, N. Round the result to the nearest integer. f VCLKDES N = ------------------------fCGMRCLK 32 MHz Example: N = ------------------- = 8 4 MHz 4. Calculate the VCO frequency, fCGMVCLK. f CGMVCLK = N x f CGMRCLK Example: fCGMVCLK = 8 x 4 MHz = 32 MHz
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5. Calculate the bus frequency, fBUS, and compare fBUS with fBUSDES. f CGMVCLK f BUS = ----------------------4 32 MHz Example: f BUS = ------------------- = 8 MHz 4 6. If the calculated fbus is not within the tolerance limits of your application, select another fBUSDES or another fRCLK. 7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear range multiplier, L. The linear range multiplier controls the frequency range of the PLL. f CGMVCLK L = round ----------------------- f NOM - 32 MHz ------------------------------- = 7 4.9152 MHz
Example: L
=
8. Calculate the VCO center-of-range frequency, fCGMVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. fCGMVRS = L x fNOM Example: fCGMVRS = 7 x 4.9152 MHz = 34.4 MHz
NOTE:
f NOM For proper operation, f CGMVRS - f CGMVCLK ---------------. 2 Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 9. Program the PLL registers accordingly: a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent of N. b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent of L.
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9.4.2.5 Special Programming Exceptions The programming method described in Programming the PLL on page 147, does not account for two possible exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these exceptions: * * A 0 value for N is interpreted the same as a value of 1. A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See Base Clock Selector Circuit on page 149.
9.4.3 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK). The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock.
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9.4.4 CGM External Connections In its typical configuration, the CGM requires seven external components. Five of these are for the crystal oscillator and two are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 9-3. Figure 9-3 shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * * * * * Crystal, X1 Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (optional)
The series resistor (RS) may not be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer's data for more information. Figure 9-3 also shows the external components for the PLL: * * Bypass capacitor, CBYP Filter capacitor, CF
Routing should be done with great care to minimize signal cross talk and noise. (See Acquisition/Lock Time Specifications on page 160 for routing information and more information on the filter capacitor's value and its effects on PLL performance).
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Clock Generator Module (CGM) I/O Signals
SIMOSCEN
CGMXCLK
OSC1
OSC2
CGMXFC
VDDA
VSS
RS* RB
VDD CF CBYP
X1
C1
C2
*RS can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer's data.
Figure 9-3. CGM External Connections
9.5 I/O Signals
The following paragraphs describe the CGM input/output (I/O) signals.
9.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier.
9.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier.
9.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin.
NOTE:
To prevent noise problems, CF should be placed as close to the CGMXFC pin as possible with minimum routing distances and no routing of other signals across the CF connection.
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9.5.4 Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage potential as the VDD pin.
NOTE:
Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package.
9.5.5 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal enables the oscillator and PLL.
9.5.6 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fCGMXCLK) and comes directly from the crystal oscillator circuit. Figure 9-3 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup.
9.5.7 CGM Base Clock Output (CGMOUT) CGMOUT is the clock output of the CGM. This signal is used to generate the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two.
9.5.8 CGM CPU Interrupt (CGMINT) CGMINT is the CPU interrupt signal generated by the PLL lock detector.
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Clock Generator Module (CGM) CGM Registers
9.6 CGM Registers
Three registers control and monitor operation of the CGM: * * * PLL control register (PCTL) PLL bandwidth control register (PBWC) PLL programming register (PPG)
9.6.1 PLL Control Register The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit.
Address: $001C Bit 7 Read: PLLIE Write: Reset: 0 0 1 0 1 1 1 1 6 PLLF PLLON BCS 5 4 3 1 2 1 1 1 Bit 0 1
= Unimplemented
Figure 9-4. PLL Control Register (PCTL) PLLIE -- PLL Interrupt Enable Bit This read/write bit enables the PLL to generate a CPU interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL CPU interrupt requests enabled 0 = PLL CPU interrupt requests disabled
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PLLF -- PLL Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates a CPU interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition
NOTE:
Do not inadvertently clear the PLLF bit. Be aware that any read or readmodify-write operation on the PLL control register clears the PLLF bit. PLLON -- PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See Base Clock Selector Circuit on page 149. Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS -- Base Clock Select Bit This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. See Base Clock Selector Circuit on page 149. Reset and the STOP instruction clear the BCS bit. 1 = CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT
NOTE:
PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off
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Clock Generator Module (CGM) CGM Registers
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. See 9.4.3 on page 149. PCTL3-PCTL0 -- Unimplemented These bits provide no function and always read as logic 1s.
9.6.2 PLL Bandwidth Control Register The PLL bandwidth control register: * * * * Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode In manual operation, forces the PLL into acquisition or tracking mode
$001D Bit 7 Read: AUTO Write: Reset: 0 0 0 0 0 0 0 0 6 LOCK ACQ XLD 5 4 3 0 2 0 1 0 Bit 0 0
Address:
= Unimplemented
Figure 9-5. PLL Bandwidth Control Register (PBWC)
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AUTO -- Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK -- Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ -- Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode XLD -- Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the crystal reference frequency is active or not. 1 = Crystal reference not active 0 = Crystal reference active
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Clock Generator Module (CGM) CGM Registers
To check the status of the crystal reference, do the following: 1. Write a logic 1 to XLD. 2. Wait N x 4 cycles. N is the VCO frequency multiplier. 3. Read XLD. The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD always reads as logic 0. Bits 3-0 -- Reserved for Test These bits enable test functions not available in user mode. To ensure software portability from development systems to user applications, software should write 0s to bits 3-0 when writing to PBWC.
9.6.3 PLL Programming Register The PLL programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO.
Address: $001E Bit 7 Read: MUL7 Write: Reset: 0 1 1 0 0 1 1 0 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 6 5 4 3 2 1 Bit 0
Figure 9-6. PLL Programming Register (PPG) MUL7-MUL4 -- Multiplier Select Bits These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N. (See Circuits on page 143 and Programming the PLL on page 147). A value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to give a default multiply value of 6.
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Table 9-3. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4 0000 0001 0010 0011 VCO Frequency Multiplier (N) 1 1 2 3
1101 1110 1111
13 14 15
NOTE:
The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1). VRS7-VRS4 -- VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency, fVRS. (See Circuits on page 143, Programming the PLL on page 147, and PLL Control Register on page 153.) VRS7-VRS4 cannot be written when the PLLON bit in the PLL control register (PCTL) is set. See Special Programming Exceptions on page 149. A value of $0 in the VCO range select bits disables the PLL and clears the BCS bit in the PCTL. (See Base Clock Selector Circuit on page 149 and Special Programming Exceptions on page 149 for more information.) Reset initializes the bits to $6 to give a default range multiply value of 6.
NOTE:
The VCO range select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1) and prevents selection of the VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock.
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Clock Generator Module (CGM) Interrupts
9.7 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupt requests from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether CPU interrupt requests are enabled or not. When the AUTO bit is clear, CPU interrupt requests from the PLL are disabled and PLLF reads as logic 0. Software should read the LOCK bit after a PLL CPU interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, CPU interrupt requests should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations.
NOTE:
Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit.
9.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
9.8.1 Wait Mode The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL.
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9.8.2 Stop Mode The STOP instruction disables the CGM and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If CGMOUT is being driven by CGMVCLK and a STOP instruction is executed; the PLL will clear the BCS bit in the PLL control register, causing CGMOUT to be driven by CGMXCLK. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear.
9.9 CGM During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Break Module on page 171). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit.
9.10 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times.
9.10.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the
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Clock Generator Module (CGM) Acquisition/Lock Time Specifications
step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5% acquisition time tolerance. If a command instructs the system to change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz 50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a -100 kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz 5 kHz. Five kHz = 5% of the 100-kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical PLL. Therefore, the definitions for acquisition and lock times for this module are: * Acquisition time, tacq, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, trk. Acquisition time is based on an initial frequency error, (fdes - forig)/fdes, of not more than 100%. In automatic bandwidth control mode (see Manual and Automatic PLL Bandwidth Modes on page 145), acquisition time expires when the ACQ bit becomes set in the PLL bandwidth control register (PBWC). Lock time, tLock, is the time the PLL takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, Lock. Lock time is based on an initial frequency error, (fdes - forig)/fdes, of not more than 100%. In automatic bandwidth control mode, lock time
*
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expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC). (See Manual and Automatic PLL Bandwidth Modes on page 145). Obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases.
9.10.2 Parametric Influences on Reaction Time Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fCGMRDV (please reference Figure 9-1 on page 142). This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency fCGMXCLK. Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a given frequency error (thus a change in charge) is proportional to the capacitor size. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. See Choosing a Filter Capacitor on page 163. Also important is the operating voltage potential applied to VDDA. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL.
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Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination.
9.10.3 Choosing a Filter Capacitor As described in Parametric Influences on Reaction Time on page 162, the external filter capacitor, CF, is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. For proper operation, the external filter capacitor must be chosen according to this equation: V DDA C F = C fact ------------------ fCGMRDV For acceptable values of Cfact, (see Electrical Specifications on page 445). For the value of VDDA, choose the voltage potential at which the MCU is operating. If the power supply is variable, choose a value near the middle of the range of possible supply values. This equation does not always yield a commonly available capacitor size, so round to the nearest available size. If the value is between two different sizes, choose the higher value for better stability. Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become unstable. Also, always choose a capacitor with a tight tolerance (20% or better) and low dissipation.
9.10.4 Reaction Time Calculation The actual acquisition and lock times can be calculated using the equations below. These equations yield nominal values under the following conditions:
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* * * * Correct selection of filter capacitor, CF (see Choosing a Filter Capacitor on page 163). Room temperature operation Negligible external leakage on CGMXFC Negligible noise
The K factor in the equations is derived from internal PLL parameters. Kacq is the K factor when the PLL is configured in acquisition mode, and Ktrk is the K factor when the PLL is configured in tracking mode. (See Acquisition and Tracking Modes on page 145).
V DDA 8 t acq = ------------------- ------------ f CGMRDV K ACQ V DDA 4 t al = ------------------- ----------- f CGMRDV K TRK t Lock = t ACQ + t AL
Note the inverse proportionality between the lock time and the reference frequency. In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (See Manual and Automatic PLL Bandwidth Modes on page 145). A certain number of clock cycles, nACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, TRK, before exiting acquisition mode. A certain number of clock cycles, nTRK, is required to ascertain that the PLL is within the lock mode entry tolerance, Lock. Therefore, the acquisition time, tACQ, is an integer multiple of nACQ/fCGMRDV, and the acquisition to lock time, tAL, is an integer multiple of nTRK/fCGMRDV. Also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than tLock as calculated above.
Advance Information 164 Clock Generator Module (CGM)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Clock Generator Module (CGM) Acquisition/Lock Time Specifications
In manual mode, it is usually necessary to wait considerably longer than tLock before selecting the PLL clock (see Base Clock Selector Circuit on page 149), because the factors described in Parametric Influences on Reaction Time on page 162, may slow the lock time considerably. When defining a limit in software for the maximum lock time, the value must allow for variation due to all of the factors mentioned in this section, especially due to the CF capacitor and application specific influences. The calculated lock time is only an indication and it is the customer's responsibility to allow enough of a guard band for their application. Prior to finalizing any software and while determining the maximum lock time, take into account all device to device differences. Typically, applications set the maximum lock time as an order of magnitude higher than the measured value. This is considered sufficient for all such device to device variation. Motorola recommends measuring the lock time of the application system by utilizing dedicated software, running in FLASH, EEPROM or RAM. This should toggle a port pin when the PLL is first configured and switched on, then again when it goes from acquisition to lock mode and finally again when the PLL lock bit is set. The resultant waveform can be captured on an oscilloscope and used to determine the typical lock time for the microcontroller and the associated external application circuit. e.g. tLOCK tACQ
Init. low
tAL
Signal on port pin tTRKComplete and Lock Set tACQComplete PLL Configured and switched on
NOTE:
The filter capacitor should be fully discharged prior to making any measurements.
Advance Information Clock Generator Module (CGM) 165
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Clock Generator Module (CGM)
Advance Information 166 Clock Generator Module (CGM)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 10. Mask Options
10.1 Contents
10.2 10.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
10.2 Introduction
This section describes the mask options and the mask option registers. The mask options are hardwired connections specified at the same time as the ROM code, which allow the user to customize the MCU. The options control the enable or disable of the following functions: * * * * * * * * * Resets caused by the LVI module Power to the LVI module Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) ROM security(1) STOP instruction Computer operating properly (COP) module enable EEPROM read protection(1) COP time-out period EEPROM reference clock source
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM/EEPROM data difficult for unauthorized users
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Mask Options
Advance Information 167
Mask Options 10.3 Functional Description
Bit 7 MORA $001F 6 5 4 3 2 1 Bit 0
Read: LVISTOP ROMSEC LVIRST Write: Reset:
LVIPWR R
SSREC R
COPRS R
STOP R
COPD R
R
R
R
Unaffected by reset
Figure 10-1. Mask Option Register A (MORA) LVISTOP -- LVI Stop Mode Enable Bit LVISTOP enables the LVI module in stop mode. See Low Voltage Inhibit (LVI) on page 195. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode ROMSEC -- ROM Security Bit ROMSEC enables the ROM security feature. Setting the ROMSEC bit prevents access to the ROM contents. 1 = ROM security enabled 0 = ROM security disabled LVIRST -- LVI Reset Enable Bit LVIRST enables the reset signal from the LVI module. See Low Voltage Inhibit (LVI). 1 = LVI module resets enabled 0 = LVI module resets disabled LVIPWR -- LVI Power Enable Bit LVIPWR enables the LVI module. See Low Voltage Inhibit (LVI). 1 = LVI module power enabled 0 = LVI module power disabled
Advance Information 168 Mask Options
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Mask Options Functional Description
SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay. 1 = STOP mode recovery after 32 CGMXCLK cycles 0 = STOP mode recovery after 4096 CGMXCLK cycles If using an external crystal oscillator, the SSREC bit should not be set. COPRS -- COP Rate Select COPRS is similar to COPL (please note that the logic is reversed) as it determines the timeout period for the COP. 1 = COP timeout period is 213 -- 24 CGMXCLK cycles. 0 = COP timeout period is 218 -- 24 CGMXCLK cycles. STOP -- STOP Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. See Computer Operating Properly (COP). 1 = COP module disabled 0 = COP module enabled
NOTE:
Extra care should be taken when selecting MOR options since not all HC08 family devices have the same options. In particular refer to the appendix on differences of previous versions of MC68HC08AZ60. It is the user's responsibility to correctly define the mask option registers.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Mask Options
Advance Information 169
Mask Options
Bit 7 MORB $FE09 Read: EEDIVCLK
6
5
4
3
2
1
Bit 0
EEMONSEC R R R
AZ60A R
Write: Reset:
R
Unaffected by reset = Unimplemented
R
= Reserved
Figure 10-2. Mask Option Register B (MORB) EEDIVCLK -- EEPROM-1 and EEPROM-2 Timebase Dividers Clock Select Bit EEDIVCLK selects the reference clock source for the EEPROM-1 and EEPROM-2 timebase dividers. See EEPROM-1 Timebase Divider Register on page 74 and EEPROM-2 Timebase Divider Register on page 94. 1 = CPU bus clock drives the EEPROM-1 and EEPROM-2 timebase dividers 0 = CGMXCLK drives the EEPROM-1 and EEPROM-2 timebase dividers EEMONSEC -- EEPROM Read Protection in Monitor Mode Bit When EEMONSEC is set, the entire EEPROM-1 and EEPROM-2 arrays cannot be acessed in monitor mode unless a valid security code is entered. 1 = EEPROM-1 and EEPROM-2 read protection in monitor mode enabled. 0 = EEPROM-1 and EEPROM-2 read protection in monitor mode disabled. AZ60A -- Device Indicator (Not user-selectable) This bit is set to a logic '1'. Extra care should be exercised when selecting mask option registers since other HC08 family parts may have different options. If in doubt, check with your local field applications representative.
Advance Information 170 Mask Options
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 11. Break Module
11.1 Contents
11.2 11.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
11.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 11.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . .173 11.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . 174 11.4.3 TIM and PIT During Break Interrupts . . . . . . . . . . . . . . . 174 11.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . 174 11.5 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.1 Break Status and Control Register (BRKSCR) . . . . . . . 175 11.5.2 Break Address Registers (BRKH and BRKL) . . . . . . . . 176 11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
11.2 Introduction
This section describes the break module. The break module can generate a break interrupt which stops normal program flow at a defined address in order to begin execution of a background program.
11.3 Features
Features of the break module include the following: * *
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Break Module
Accessible I/O registers during the break interrupt CPU-generated break Interrupts
Advance Information 171
Break Module
* * Software-generated break interrupts COP disabling during break interrupts
11.4 Functional Description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU-generated address (the address in the program counter) matches the contents of the break address registers. Software writes a `1' to the BRKA bit in the break status and control register (BRKSCR).
When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Figure 11-1 shows the structure of the break module.
Advance Information 172 Break Module
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Break Module Functional Description
IAB[15:8]
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BKPT (TO SIM)
IAB[7:0]
Figure 11-1. Break Module Block Diagram Table 11-1. Break I/O Register Summary
Register Name Break Address Register High (BRKH) Break Address Register Low (BRKL) reak Status/Control Register (BRKSCR) Bit 7 Bit 15 Bit 7 6 14 6 5 13 5 0 BRKE BRKA 4 12 4 0 3 11 3 0 2 10 2 0 1 9 1 0 Bit 0 Addr.
Bit 8 $FE0C Bit 0 $FE0D 0 $FE0E
= Unimplemented
11.4.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See System Integration Module (SIM) on page 117, and the Break Interrupts subsection for each module.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Break Module
Advance Information 173
Break Module
11.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
11.4.3 TIM and PIT During Break Interrupts A break interrupt stops the timer counter.
11.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VHI is present on the RST pin.
11.5 Break Module Registers
Three registers control and monitor operation of the break module: * * * Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL)
Advance Information 174 Break Module
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Break Module Break Module Registers
11.5.1 Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits.
Bit 7 BRKSCR $FE0E Read: 6 5 4 3 2 1 Bit 0
0 BRKE BRKA
0 0
0
0
0
0
0
Write: Reset: 0 0 0 0 0 0
= Unimplemented
Figure 11-2. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. BRKE is cleared by writing a `0' to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a `1' to BRKA generates a break interrupt. BRKA is cleared by writing a `0' to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Break Module
Advance Information 175
Break Module
11.5.2 Break Address Registers (BRKH and BRKL) The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Bit 7 BRKH $FE0C Read: 6 5 4 3 2 1 Bit 0
Bit 15
Write: Reset: 0 Bit 7
14
0 6
13
0 5
12
0 4
11
0 3
10
0 2
9
0 1
Bit 8
0 Bit 0
BRKL $FE0D
Read:
Bit 7
Write: Reset: 0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Figure 11-3. Break Address Registers (BRKH and BRKL)
11.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
11.6.1 Wait Mode If enabled, the break module is active in wait mode. The SIM break wait bit (BW) in the SIM break status register indicates whether wait was exited by a break interrupt. If so, the user can modify the return address on the stack by subtracting one from it. (See System Integration Module (SIM) on page 117).
11.6.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states.
Advance Information 176 Break Module
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 12. Monitor ROM (MON)
12.1 Contents
12.2 12.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
12.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 12.4.1 Entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . .180 12.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 12.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 12.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 12.4.4.1 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 12.4.5 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 12.4.6 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
12.2 Introduction
This section describes the monitor ROM (MON08). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer.
12.3 Features
Features of the monitor ROM include the following: * * * *
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Monitor ROM (MON)
Normal User-Mode Pin Functionality One Pin Dedicated to Serial Communication Between Monitor ROM and Host Computer Standard Mark/Space Non-Return-to-Zero (NRZ) Communication with Host Computer Up to 28.8K Baud Communication with Host Computer
Advance Information 177
Monitor ROM (MON)
* * * * Execution of Code in RAM or ROM EEPROM Programming ROM Security (Read Protection)(1) EEPROM Read Protection(1)
12.4 Functional description
The monitor ROM receives and executes commands from a host computer. Figure 12-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard RS-232 interface. While simple monitor commands can access any memory address, the MC68HC08AZ60A has optional ROM/EEPROM read protection features to prevent external viewing of the contents of ROM/EEPROM (see Mask Options on page 167). Proper procedures must be followed to verify ROM/EEPROM content. Access to the ROM/EEPROM is denied to unauthorized users of customer specified software with read protection features enabled. See Security. In monitor mode, the MCU can execute host-computer code in RAM while all MCU pins except PTA0 retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pull-up resistor.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM/EEPROM data difficult for unauthorized users
Advance Information 178 Monitor ROM (MON)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Monitor ROM (MON) Functional description
VDD 68HC08 10 k RST 0.1 F
VHI 1 K IRQ TBD
VDDA
VDDA CGMXFC
1 10 F + 3 4 10 F +
MC145407
20 + 18 17 + 10 F 20 pF X1 4.9152 MHz 20 pF 10 F
0.1 F
OSC1 10 M OSC2 VSSA VSS
2
19
DB-25 2 3 7
5 6
16 15 VDD 0.1 F VDD 1 2 6 4 MC68HC125 14 3 5 VDD 10 k A (See NOTE.) B VDD 10 k PTA0
VDD
PTC3 VDD 10 k PTC0 PTC1
7
NOTE: Position A -- Bus clock = CGMXCLK / 4 or CGMVCLK / 4 Position B -- Bus clock = CGMXCLK / 2
Figure 12-1. Monitor Mode Circuit
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Monitor ROM (MON) Advance Information 179
Monitor ROM (MON)
12.4.1 Entering monitor mode Table 12-1 shows the pin conditions for entering monitor mode. Table 12-1. Mode Selection
PTC0 Pin PTC1 Pin PTA0 Pin PTC3 Pin IRQ Pin Mode CGMOUT Bus Frequency
VHI(1)
1
0
1
1
Monitor
CGMXCLK CGMVCLK ---------------------------- or ---------------------------2 2
CGMOUT ------------------------2 CGMOUT ------------------------2
VHI(1)
1
0
1
0
Monitor
CGMXCLK
1. For VHI, 5.0 Volt DC Electrical Characteristics on page 448, and Maximum Ratings on page 446.
Enter monitor mode by either * * Executing a software interrupt instruction (SWI) or Applying a `0' and then a `1' to the RST pin.
Once out of reset, the MCU waits for the host to send eight security bytes (see Security on page 186). After the security bytes, the MCU sends a break signal (10 consecutive `0's) to the host computer, indicating that it is ready to receive a command. Monitor mode uses alternate vectors for reset, SWI, and break interrupt. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. The COP module is disabled in monitor mode as long as VHI (see Electrical Specifications on page 445), is applied to either the IRQ pin or the RST pin. See System Integration Module (SIM) on page 117 for more information on modes of operation.
NOTE:
Holding the PTC3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator. The CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
Advance Information 180 Monitor ROM (MON)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Monitor ROM (MON) Functional description
Table 12-2 is a summary of the differences between user mode and monitor mode. Table 12-2. Mode Differences
Functions Modes COP Enabled Disabled(1) Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
User Monitor
1. If the high voltage (VHI) is removed from the IRQ and/or RESET pin while in monitor mode, the SIM asserts its COP enable output. The COP is enabled or disabled by the COPD bit in the configuration register. See 5.0 Volt DC Electrical Characteristics.
12.4.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See Figure 12-2 and Figure 12-3).
START BIT NEXT START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT
Figure 12-2. Monitor Data Format
$A5
START BIT START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT STOP BIT
NEXT START BIT
BREAK
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
NEXT START BIT
Figure 12-3. Sample Monitor Waveforms The data transmit and receive rate can be anywhere up to 28.8 KBaud. Transmit and receive baud rates must be identical.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Monitor ROM (MON)
Advance Information 181
Monitor ROM (MON)
12.4.3 Echoing The monitor ROM immediately echoes each received byte back to the PTA0 pin for error checking, as shown in Figure 12-4.
SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Figure 12-4. Read Transaction Any result of a command appears after the echo of the last byte of the command.
12.4.4 Break Signal A break signal is a start bit followed by nine low bits. This is shown in Figure 12-4. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits before echoing the break signal.
MISSING STOP BIT TWO-STOP-BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 12-5. Break Transaction
Advance Information 182 Monitor ROM (MON)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Monitor ROM (MON) Functional description
12.4.4.1 Commands The monitor ROM uses the following commands: * * * * * * READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program) Table 12-3. READ (Read Memory) Command
Description Operand Data returned Opcode Read byte from memory Specifies 2-byte address in high byte:low byte order Returns contents of specified address $4A
Command sequence
SENT TO MONITOR READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA
ECHO
RESULT
Table 12-4. WRITE (Write Memory) Command
Description Operand Data returned Opcode Write byte to memory Specifies 2-byte address in high byte:low byte order; low byte followed by data byte None $49
Command sequence
SENT TO MONITOR WRITE WRITE ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA DATA
ECHO
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Monitor ROM (MON)
Advance Information 183
Monitor ROM (MON)
Table 12-5. IREAD (Indexed Read) Command
Description Operand Data returned Opcode Read next 2 bytes in memory from last address accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A
Command sequence
SENT TO MONITOR IREAD IREAD DATA DATA
ECHO
RESULT
Table 12-6. IWRITE (Indexed Write) Command
Description Operand Data returned Opcode Write to last address accessed + 1 Specifies single data byte None $19
Command sequence
SENT TO MONITOR IWRITE IWRITE DATA DATA
ECHO
Advance Information 184 Monitor ROM (MON)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Monitor ROM (MON) Functional description
A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64K byte memory map. Table 12-7. READSP (Read Stack Pointer) Command
Description Operand Data returned Opcode Reads stack pointer None Returns stack pointer in high byte:low byte order $0C
Command sequence
SENT TO MONITOR READSP READSP SP HIGH SP LOW
ECHO
RESULT
Table 12-8. RUN (Run User Program) Command
Description Operand Data returned Opcode Executes RTI instruction None None $28
Command sequence
SENT TO MONITOR RUN RUN
ECHO
12.4.5 Baud Rate The MC68HC08AZ60A features a monitor mode which is optimised to operate with either a 4.9152MHz crystal clock source (or multiples of 4.9152MHz) or a 4MHz crystal (or multiples of 4MHz). This supports designs which use the MSCAN08 module, which is generally clocked from a 4MHz, 8MHz or 16MHz internal reference clock. The table below
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Monitor ROM (MON)
Advance Information 185
Monitor ROM (MON)
outlines the available baud rates for a range of crystals and how they can match to a PC baud rate.
Baud rate Clock freq 32kHz 1MHz 2MHz 4MHz 4.194MHz 4.9152MHz 8MHz 16MHz PTC3=0 57.97 1811.59 3623.19 7246.37 7597.83 8904.35 14492.72 28985.51 PTC3=1 28.98 905.80 1811.59 3623.19 3798.91 4452.17 7246.37 14492.75 Closest PC baud PC PTC3=0 57.6 1800 3600 7200 7680 8861 14400 28800 PTC3=1 28.8 900 1800 3600 3840 4430 7200 14400 Error % PTC3=0 0.64 0.64 0.64 0.64 1.08 0.49 0.64 0.64 PTC3=1 0.63 0.64 0.64 0.64 1.08 0.50 0.64 0.64
Care should be taken when setting the baud rate since incorrect baud rate setting can result in communications failure.
12.4.6 Security Security features discourage unauthorized reading of ROM/EEPROM locations while in monitor mode. The host can bypass the security features at monitor mode entry by sending eight security bytes that match the byte locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain user-defined data.
NOTE:
Do not leave locations $FFF6-$FFFD blank. For security reasons, enter data at locations $FFF6-$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PA0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security features and can read all ROM/EEPROM locations and execute code from ROM. Security remains bypassed until a power-on reset occurs. After the host bypasses security, any reset other than a power-on reset requires the host to send another eight
Advance Information 186 Monitor ROM (MON)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Monitor ROM (MON) Functional description
bytes. If the reset was not a power-on reset, security remains bypassed regardless of the data that the host sends. If the received bytes do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security features. The MCU remains in monitor mode, but reading ROM/EEPROM locations returns undefined data, and trying to execute code from ROM causes an illegal address reset. After the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. After receiving the eight security bytes from the host, the MCU transmits a break character signalling that it is ready to receive a command.
NOTE:
The MCU does not transmit a break character until after the host sends the eight security bytes.
VDD 4096 + 32 CGMXCLK CYCLES RST 24 BUS CYCLES (MINIMUM) Command 1 Byte 2 Echo Byte 8 Echo 2 Break 4 1 Command Echo Byte 1 Byte 2 Byte 8 1
FROM HOST PA0 1 Byte 1 Echo FROM MCU 4
NOTE: 1 = Echo delay (2 bit times) 2 = Data return delay (2 bit times) 4 = Wait 1 bit time before sending next byte.
Figure 12-6. Monitor Mode Entry Timing
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Monitor ROM (MON)
Advance Information 187
Monitor ROM (MON)
Advance Information 188 Monitor ROM (MON)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 13. Computer Operating Properly (COP)
13.1 Contents
13.2 13.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.4.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 13.4.3 COPCTL Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4.7 COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 192 13.5 13.6 13.7 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . 193 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.8.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.8.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 13.9 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . 194
13.2 Introduction
This section describes the computer operating properly (COP) module, a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. COP resets can be prevented by periodically clearing the COP counter.
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Advance Information 189
Computer Operating Properly (COP) 13.3 Functional Description
Figure 13-1 shows the structure of the COP module.
12-BIT COP PRESCALER CGMXCLK CLEAR ALL STAGES CLEAR STAGES 4-12
STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE
RESET RESET STATUS REGISTER 6-BIT COP COUNTER
COPD FROM MORA RESET COPCTL WRITE CLEAR COP COUNTER
COPRS FROM MORA
Figure 13-1. COP Block Diagram Table 13-1. COP I/O Register Summary
Register Name COP Control Register (COPCTL) Bit 7 6 5 4 3 2 1 Bit 0 Addr. $FFFF
The COP counter is a free-running 6-bit counter preceded by a12-bit prescaler. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 213 - 24, or 218 - 24 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS in
Advance Information 190 Computer Operating Properly (COP) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Computer Operating Properly (COP) I/O Signals
MORA. When COPRS = 0, a 4.9152 MHz crystal, gives a COP timeout period of 53.3ms. Writing any value to location $FFFF before overflow occurs prevents a COP reset by clearing the COP counter and stages 4 through 12 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the SIM reset status register (SRSR). See SIM Reset Status Register (SRSR). In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held at VHi. During the break state, VHi on the RST pin disables the COP.
NOTE:
Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
13.4 I/O Signals
The following paragraphs describe the signals shown in Figure 13-1.
13.4.1 CGMXCLK CGMXCLK is the crystal oscillator output signal. The CGMXCLK frequency is equal to the crystal frequency.
13.4.2 STOP Instruction The STOP instruction clears the COP prescaler.
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Advance Information 191
Computer Operating Properly (COP)
13.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see COP Control Register (COPCTL) on page 193), clears the COP counter and clears bits 12 - 4 of the COP prescaler. Reading the COP control register returns the reset vector.
13.4.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
13.4.5 Internal Reset An internal reset clears the COP prescaler and the COP counter.
13.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler.
13.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the mask option register (MORA). See Mask Options.
13.4.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit, COPRS in the MORA register (see Figure 10-1 on page 168).
Advance Information 192 Computer Operating Properly (COP)
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Computer Operating Properly (COP) COP Control Register (COPCTL)
13.5 COP Control Register (COPCTL)
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Bit 7 COPCTL $FFFF Read: Write: Reset: 6 5 4 3 2 1 Bit 0
Low byte of reset vector Clear COP counter Unaffected by reset
Figure 13-2. COP Control Register (COPCTL)
13.6 Interrupts
The COP does not generate CPU interrupt requests.
13.7 Monitor Mode
The COP is disabled in monitor mode when VHI is present on the IRQ pin or on the RST pin.
13.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
13.8.1 WAIT Mode The COP continues to operate during WAIT mode. To prevent a COP reset during WAIT mode, the COP counter should be cleared periodically in a CPU interrupt routine.
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Advance Information 193
Computer Operating Properly (COP)
13.8.2 STOP Mode STOP mode turns off the CGMXCLK input to the COP and clears the COP prescaler. The COP should be serviced immediately before entering or after exiting STOP mode to ensure a full COP timeout period after entering or exiting STOP mode. The STOP bit in the mask option register (MOR) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, the STOP instruction should be disabled by programming the STOP bit to `0'.
13.9 COP Module During Break Interrupts
The COP is disabled during a break interrupt when VHI is present on the RST pin.
Advance Information 194 Computer Operating Properly (COP)
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Advance Information -- MC68HC08AZ60A
Section 14. Low Voltage Inhibit (LVI)
14.1 Contents
14.2 14.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
14.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 14.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.4.3 False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . 198 14.5 14.6 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . 198 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
14.2 Introduction
This section describes the low-voltage inhibit module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage. Note that the LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application VDD voltage collapsing completely to an unsafe level. Is is not intended that users operate the microcontroller at lower than the specified operating voltage, VDD.
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Advance Information 195
Low Voltage Inhibit (LVI) 14.3 Features
Features of the LVI module include the following: * * * Programmable LVI reset Programmable power consumption Digital filtering of VDD pin level
NOTE:
If a low voltage interrupt (LVI) occurs during programming of EEPROM memory, then adequate programming time may not have been allowed to ensure the integrity and retention of the data. It is the responsibility of the user to ensure that in the event of an LVI any addresses being programmed receive specification programming conditions.
14.4 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to monitor VDD voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when VDD falls below a voltage, LVITRIPF, and remains at or below that level for 9 or more consecutive CPU cycles. Note that short VDD spikes may not trip the LVI. It is the user's responsibility to ensure a clean VDD signal within the specified operating voltage range if normal microcontroller operation is to be guaranteed. LVISTOP enables the LVI module during stop mode. This will ensure when the STOP instruction is implemented the LVI will continue to monitor the voltage level on VDD. LVIPWR, LVIRST and LVISTOP are mask options. See Mask Options on page 167. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, LVITRIPR. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
Advance Information 196 Low Voltage Inhibit (LVI)
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Low Voltage Inhibit (LVI) Functional Description
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
VDD
LVIPWR FROM MORA CPU CLOCK LOW VDD DETECTOR VDD > LVITRIP = 0 VDD < LVITRIP = 1 Stop Mode Filter Bypass ANLGTRIP LVISTOP FROM MORA LVIOUT VDD DIGITAL FILTER FROM MORA LVIRST LVI RESET
Figure 14-1. LVI Module Block Diagram Table 14-1. LVI I/O Register Summary
Register Name Bit 7 6 5 4 3 2 1 Bit 0 Addr. $FE0F = Unimplemented
LVI Status Register (LVISR) LVIOUT
14.4.1 Polled LVI Operation In applications that can operate at VDD levels below the LVITRIPF level, software can monitor VDD by polling the LVIOUT bit. In the mask option register, the LVIPWR bit must be at logic `1' to enable the LVI module and the LVIRST bit must be at logic `0' to disable LVI resets.
14.4.2 Forced Reset Operation In applications that require VDD to remain above the LVITRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls to the LVITRIPF level and remains at or below that level for 9 or more consecutive CPU cycles. In the mask option register, the LVIPWR and
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Low Voltage Inhibit (LVI) Advance Information 197
Low Voltage Inhibit (LVI)
LVIRST bits must be at `1' to enable the LVI module and to enable LVI resets.
14.4.3 False Reset Protection The VDD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI module to reset the MCU,VDD must remain at or below the LVITRIPF level for 9 or more consecutive CPU cycles. VDD must be above LVITRIPR for only one CPU cycle to bring the MCU out of reset.
14.5 LVI Status Register (LVISR)
The LVI status register flags VDD voltages below the LVITRIPF level.
Bit 7 LVISR $FE0F Read: LVIOUT Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI Status Register (LVISR) LVIOUT -- LVI Output Bit This read-only flag becomes set when VDD falls below the LVITRIPF voltage for 32-40 CGMXCLK cycles. (See Table 14-2). Reset clears the LVIOUT bit.
Advance Information 198 Low Voltage Inhibit (LVI)
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Low Voltage Inhibit (LVI) LVI Interrupts
Table 14-2. LVIOUT Bit Indication
VDD at level: VDD > LVITRIPR VDD < LVITRIPF VDD < LVITRIPF VDD < LVITRIPF LVITRIPF < VDD < LVITRIPR for number of CGMXCLK cycles: ANY < 32 CGMXCLK cycles between 32 & 40 CGMXCLK cycles > 40 CGMXCLK cycles ANY LVIOUT 0 0 0 or 1 1 Previous Value
14.6 LVI Interrupts
The LVI module does not generate interrupt requests.
14.7 Low-Power Modes
The WAIT instruction puts the MCU in low-power-consumption standby mode.
14.7.1 WAIT Mode When the LVIPWR mask option is programmed to `1', the LVI module is active after a WAIT instruction. When the LVIRST mask option is programmed to `1', the LVI module can generate a reset and bring the MCU out of WAIT mode.
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Advance Information 199
Low Voltage Inhibit (LVI)
14.7.2 Stop Mode With LVISTOP=1 and LVIPWR=1 in the MORA register, the LVI module will be active after a STOP instruction. Because CPU clocks are disabled during stop mode, the LVI trip must bypass the digital filter to generate a reset and bring the MCU out of stop. With the LVIPWR bit in the MORA register at a logic 1 and the LVISTOP bit at a logic 0, the LVI module will be inactive after a STOP instruction.
Advance Information 200 Low Voltage Inhibit (LVI)
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Advance Information -- MC68HC08AZ60A
Section 15. External Interrupt Module (IRQ)
15.1 Contents
15.2 15.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
15.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 15.4.1 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 15.5 15.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . 206 IRQ Status and Control Register (ISCR). . . . . . . . . . . . . . .206
15.2 Introduction
The IRQ module provides the nonmaskable interrupt input.
15.3 Features
Features of the IRQ module include the following: * * * * * Dedicated external interrupt pins (IRQ) IRQ interrupt control bit Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge
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Advance Information 201
External Interrupt Module (IRQ) 15.4 Functional Description
A `0' applied to any of the external interrupt pins can latch a CPU interrupt request. Figure 15-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following occurs: * Vector fetch -- a vector fetch automatically generates an interrupt acknowledge signal which clears the latch that caused the vector fetch. Software clear -- software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (ISCR). Writing a logic `1' to the ACK bit clears the IRQ latch. Reset -- a reset automatically clears the interrupt latch.
*
*
ACK
INTERNAL ADDRESS BUS
VECTOR FETCH DECODER
TO CPU FOR BIL/BIH INSTRUCTIONS
VDD D IRQ CLR Q SYNCHRONIZER
IRQF IRQ INTERRUPT REQUEST
CK IRQ LATCH IMASK
MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 15-1. IRQ Module Block Diagram The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be both falling-edge and low-level-triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ pin.
Advance Information 202 External Interrupt Module (IRQ)
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External Interrupt Module (IRQ) Functional Description
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs. When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to `1'
The vector fetch or software clear may occur before or after the interrupt pin returns to `1'. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. Table 15-1. IRQ I/O Register Summary
Register Name Read: IRQ Status/Control Register (ISCR) Write: R R R R R ACK Bit 7 0 6 0 5 0 4 0 3 IRQF 2 0 IMASK MODE $001A 1 Bit 0 Addr.
R
= Reserved
When set, the IMASK bit in the ISCR masks all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. See Figure 152.
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Advance Information 203
External Interrupt Module (IRQ)
.
FROM RESET
YES
I BIT SET?
NO
INTERRUPT?
YES
NO STACK CPU REGISTERS. SET I BIT. LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT INSTRUCTION.
SWI INSTRUCTION?
YES
NO
RTI INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO EXECUTE INSTRUCTION.
Figure 15-2. IRQ Interrupt Flowchart
Advance Information 204 External Interrupt Module (IRQ)
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External Interrupt Module (IRQ) Functional Description
15.4.1 IRQ Pin A `0' on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur to clear the IRQ latch: * Vector fetch or software clear -- a vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic `1' to the ACK bit in the interrupt status and control register (ISCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ pin to logic `1' -- as long as the IRQ pin is at logic `0', the IRQ latch remains set.
*
The vector fetch or software clear and the return of the IRQ pin to logic `1' may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic `0'. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. The BIH or BIL instruction is used to read the logic level on the IRQ pin.
NOTE:
When using the level-sensitive interrupt trigger, false interrupts can be avoided by masking interrupt requests in the interrupt routine.
Advance Information External Interrupt Module (IRQ) 205
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External Interrupt Module (IRQ) 15.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ interrupt latch can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latches during the break state. See SIM Break Flag Control Register (SBFCR). To allow software to clear the IRQ latch during a break interrupt, write a logic '1' to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic `0' to the BCFE bit. With BCFE at logic `0' (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
15.6 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR performs the following functions: * * * *
Address:
Indicates the state of the IRQ interrupt flag Clears the IRQ interrupt latch Masks IRQ interrupt requests Controls triggering sensitivity of the IRQ interrupt pin
$001A Bit 7 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 IRQF R 0 2 0 IMASK MODE 0 ACK 0 0 1 Bit 0
Read: Write: Reset:
0 R 0 R
Figure 15-3. IRQ Status and Control Register (ISCR)
Advance Information 206 External Interrupt Module (IRQ)
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External Interrupt Module (IRQ) IRQ Status and Control Register (ISCR)
IRQF -- IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic `1' to this write-only bit clears the IRQ latch. ACK always reads as logic `0'. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic `1' to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
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Advance Information 207
External Interrupt Module (IRQ)
Advance Information 208 External Interrupt Module (IRQ)
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Advance Information -- MC68HC08AZ60A
Section 16. Serial Communications Interface (SCI)
16.1 Contents
16.2 16.3 16.4 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 16.5.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.5.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 16.5.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 16.5.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . 214 16.5.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 16.5.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.5.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . 219 16.5.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 219 16.5.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 16.5.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 16.5.3.2 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . .222 16.5.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 16.5.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.5.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.5.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 16.5.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16.5.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 16.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 16.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 16.7 SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . 230
16.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 16.8.1 PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . . 231 16.8.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . 231
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Serial Communications Interface (SCI)
16.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 16.9.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 16.9.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 16.9.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.9.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 16.9.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.9.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.9.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . 245
16.2 Introduction
The SCI allows asynchronous communications with peripheral devices and other MCUs.
16.3 Features
The SCI module's features include: * * * * * * * * Full Duplex Operation Standard Mark/Space Non-Return-to-Zero (NRZ) Format 32 Programmable Baud Rates Programmable 8-Bit or 9-Bit Character Length Separately Enabled Transmitter and Receiver Separate Receiver and Transmitter CPU Interrupt Requests Programmable Transmitter Output Polarity Two Receiver Wakeup Methods: - Idle Line Wakeup - Address Mark Wakeup * Interrupt-Driven Operation with Eight Interrupt Flags: - Transmitter Empty - Transmission Complete - Receiver Full
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Serial Communications Interface (SCI) Pin Name Conventions
- Idle Receiver Input - Receiver Overrun - Noise Error - Framing Error - Parity Error * * * Receiver Framing Error Detection Hardware Parity Checking 1/16 Bit-Time Noise Detection
16.4 Pin Name Conventions
The generic names of the SCI input/output (I/O) pins are: * * RxD (receive data) TxD (transmit data)
SCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 16-1 shows the full names and the generic names of the SCI I/O pins.The generic pin names appear in the text of this section. Table 16-1. Pin Name Conventions
Generic Pin Names Full Pin Names RxD PTE1/RxD TxD PTE0/TxD
16.5 Functional Description
Figure 16-1 shows the structure of the SCI module. The SCI allows fullduplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
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INTERNAL BUS
TRANSMITTER INTERRUPT CONTROL
SCI DATA REGISTER RECEIVE SHIFT REGISTER
SCI DATA REGISTER RECEIVER INTERRUPT CONTROL ERROR INTERRUPT CONTROL TRANSMIT SHIFT REGISTER TXINV
RxD
TxD
SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCTE TC SCRF IDLE OR NF FE PE LOOPS LOOPS WAKEUP CONTROL RECEIVE CONTROL BKF RPF BAUD RATE GENERATOR FLAG CONTROL M WAKE ILTY CGMXCLK PEN PTY DATA SELECTION CONTROL ENSCI
R8 T8
ORIE NEIE FEIE PEIE
TRANSMIT CONTROL
ENSCI
/4
PRESCALER
/ 16
Figure 16-1. SCI Module Block Diagram
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Register Name SCI Control Register 1 (SCC1)
SCI Control Register 2 (SCC2)
SCI Control Register 3 (SCC3)
SCI Status Register 1 (SCS1)
SCI Status Register 2 (SCS2)
SCI Data Register (SCDR)
SCI Baud Rate Register (SCBR)
Bit 7 Read: LOOPS Write: Reset: 0 Read: SCTIE Write: Reset: 0 Read: R8 Write: Reset: U Read: SCTE Write: Reset: 1 Read: 0 Write: Reset: 0 Read: R7 Write: T7 Reset: Read: 0 Write: Reset: 0
6 ENSCI 0 TCIE 0 T8 U TC 1 0 0 R6 T6 0 0
5 TXINV 0 SCRIE 0 R 0 SCRF 0 0 0 R5 T5 SCP1 0
4 M 0 ILIE 0 R 0 IDLE 0 0
3 WAKE 0 TE 0 ORIE 0 OR 0 0
2 ILTY 0 RE 0 NEIE 0 NF 0 0 0 R2 T2 SCR2 0 R = Reserved
1 PEN 0 RWU 0 FEIE 0 FE 0 BKF 0 R1 T1 SCR1 0
Bit 0 PTY 0 SBK 0 PEIE 0 PE 0 RPF 0 R0 T0 SCR0 0
0 0 R4 R3 T4 T3 Unaffected by Reset SCP0 0 U = Unaffected R 0
= Unimplemented
Figure 16-2. SCI I/O Register Summary
Table 16-2. SCI I/O Register Address Summary
Register Address SCC1 $0013 SCC2 $0014 SCC3 $0015 SCS1 $0016 SCS2 $0017 SCDR $0018 SCBR $0019
16.5.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 16-3.
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8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
PARITY OR DATA BIT BIT 7 STOP BIT
NEXT START BIT
9-BIT DATA FORMAT (BIT M IN SCC1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
PARITY OR DATA BIT BIT 7 BIT 8 STOP BIT
NEXT START BIT
Figure 16-3. SCI Data Formats
16.5.2 Transmitter Figure 16-4 shows the structure of the SCI transmitter. 16.5.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 16.5.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). 2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register 2 (SCC2). 3. Clear the SCI transmitter empty bit (SCTE) by first reading SCI status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the
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preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins.
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INTERNAL BUS
/4
CGMXCLK SCP1 SCP0 SCR1 SCR2 SCR0 TRANSMITTER CPU INTERRUPT REQUEST
PRESCALER
BAUD DIVIDER
/ 16
SCI DATA REGISTER
H
8
7
6
5
4
3
2
1
0
START L
STOP
11-BIT TRANSMIT SHIFT REGISTER
TxD
TXINV
M PEN PTY PARITY GENERATION LOAD FROM SCDR
MSB
SHIFT ENABLE
T8
TRANSMITTER CONTROL LOGIC
SCTE SCTE SCTIE TC TCIE
PREAMBLE (ALL ONES)
LOOPS SCTIE TC TCIE ENSCI TE
Figure 16-4. SCI Transmitter
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BREAK (ALL ZEROS) SBK
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Register Name Read: SCI Control Register 1 (SCC1) Write: Reset: Read: SCI Control Register 2 (SCC2) Write: Reset: Read: SCI Control Register 3 (SCC3) Write: Reset: Read: SCI Status Register 1 (SCS1) Write: Reset: Read: SCI Data Register (SCDR) Write: Reset: Read: SCI Baud Rate Register (SCBR) Write: Reset:
Bit 7 LOOPS 0 SCTIE 0 R8
6 ENSCI 0 TCIE 0 T8 U TC
5 TXINV 0 SCRIE 0 R 0 SCRF
4 M 0 ILIE 0 R 0 IDLE
3 WAKE 0 TE 0 ORIE 0 OR
2 ILTY 0 RE 0 NEIE 0 NF
1 PEN 0 RWU 0 FEIE 0 FE
Bit 0 PTY 0 SBK 0 PEIE 0 PE
U SCTE
1 R7 T7
1 R6 T6
0 R5 T5
0 R4 T4
0 R3 T3
0 R2 T2
0 R1 T1
0 R0 T0
Unaffected by Reset 0 0 SCP1 0 SCP0 0 R 0 SCR2 0 SCR1 0 SCR0 0
0
0
= Unimplemented
U = Unaffected
R = Reserved
Figure 16-5. SCI Transmitter I/O Register Summary
Table 16-3. SCI Transmitter I/O Address Summary
Register Address SCC1 $0013 SCC2 $0014 SCC3 $0015 SCS1 $0016 SCDR $0018 SCBR $0019
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16.5.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has the following effects on SCI registers: * * * * * * Sets the framing error bit (FE) in SCS1 Sets the SCI receiver full bit (SCRF) in SCS1 Clears the SCI data register (SCDR) Clears the R8 bit in SCC3 Sets the break flag bit (BKF) in SCS2 May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
16.5.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted.
NOTE:
When a break sequence is followed immediately by an idle character, this SCI design exhibits a condition in which the break character length is reduced by one half bit time. In this instance, the break sequence will
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consist of a valid start bit, eight or nine data bits (as defined by the M bit in SCC1) of logic 0 and one half data bit length of logic 0 in the stop bit position followed immediately by the idle character. To ensure a break character of the proper length is transmitted, always queue up a byte of data to be transmitted while the final break sequence is in progress.
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. A good time to toggle the TE bit for a queued idle character is when the SCTE bit becomes set and just before writing the next byte to the SCDR.
16.5.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. (See 16.9.1 SCI Control Register 1.) 16.5.2.6 Transmitter Interrupts The following conditions can generate CPU interrupt requests from the SCI transmitter: * SCI transmitter empty (SCTE) -- The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. Transmission complete (TC) -- The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests.
*
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16.5.3 Receiver Figure 16-6 shows the structure of the SCI receiver.
INTERNAL BUS
SCR1 SCP1 SCP0 SCR2 SCR0 START 0 L RWU PRESCALER BAUD DIVIDER SCI DATA REGISTER
STOP
/4
CGMXCLK
/ 16
DATA RECOVERY
11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1
RxD
H ALL ONES
BKF RPF ERROR CPU INTERRUPT REQUEST
ALL ZEROS
CPU INTERRUPT REQUEST
M WAKE ILTY PEN PTY WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE
MSB
SCRF IDLE
R8
ILIE
SCRIE
OR ORIE NF NEIE FE FEIE PE PEIE
OR ORIE NF NEIE FE FEIE PE PEIE
Figure 16-6. SCI Receiver Block Diagram
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Serial Communications Interface (SCI) Functional Description
Register Name SCI Control Register 1 (SCC1) Read: Write: Reset: SCI Control Register 2 (SCC2) Read: Write: Reset: SCI Control Register 3 (SCC3) Read: Write: Reset: SCI Status Register 1 (SCS1) Read: Write: Reset: SCI Status Register 2 (SCS2) Read: Write: Reset: SCI Data Register (SCDR) Read: Write: Reset: SCI Baud Rate Register (SCBR) Read: Write: Reset:
Bit 7 LOOPS 0 SCTIE 0 R8
6 ENSCI 0 TCIE 0 T8 U TC
5 TXINV 0 SCRIE 0 R 0 SCRF
4 M 0 ILIE 0 R 0 IDLE
3 WAKE 0 TE 0 ORIE 0 OR
2 ILTY 0 RE 0 NEIE 0 NF
1 PEN 0 RWU 0 FEIE 0 FE
Bit 0 PTY 0 SBK 0 PEIE 0 PE
U SCTE
1 0
1 0
0 0
0 0
0 0
0 0
0 BKF
0 RPF
0 R7 T7
0 R6 T6
0 R5 T5
0 R4 T4
0 R3 T3
0 R2 T2
0 R1 T1
0 R0 T0
Unaffected by Reset 0 0 SCP1 0 SCP0 0 R 0 SCR2 0 SCR1 0 SCR0 0
0
0
= Unimplemented
U = Unaffected
R
= Reserved
Figure 16-7. SCI I/O Receiver Register Summary
Table 16-4. SCI Receiver I/O Address Summary
Register Address SCC1 $0013 SCC2 $0014 SCC3 $0015 SCS1 $0016 SCS2 $0017 SCDR $0018 SCBR $0019
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16.5.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 16.5.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. 16.5.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following times (see Figure 16-8): * * After every start bit After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
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RxD
START BIT
LSB
SAMPLES
START BIT QUALIFICATION
START BIT DATA VERIFICATION SAMPLING
RT CLOCK RT CLOCK STATE RT CLOCK RESET RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4
Figure 16-8. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 16-5 summarizes the results of the start bit verification samples. Table 16-5. Start Bit Verification
RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
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To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 16-6 summarizes the results of the data bit samples. Table 16-6. Data Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0
NOTE:
The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 16-7 summarizes the results of the stop bit samples. Table 16-7. Stop Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0
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16.5.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 16.5.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 16-9 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
MSB
STOP
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 16-9. Slow Data
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For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 16-9, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154 - 147 x 100 = 4.54% ------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 16-9, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 - 163 x 100 = 4.12% ------------------------170
Fast Data Tolerance Figure 16-10 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 16-10. Fast Data
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For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 16-10, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154 - 160 x 100 = 3.90%. ------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 16-10, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170 - 176 x 100 = 3.53%. ------------------------170 16.5.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: * Address mark -- An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and
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processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. * Idle input line condition -- When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit.
NOTE:
With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately.
16.5.3.7 Receiver Interrupts The following sources can generate CPU interrupt requests from the SCI receiver: * SCI receiver full (SCRF) -- The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. Idle input (IDLE) -- The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests.
*
16.5.3.8 Error Interrupts The following receiver error flags in SCS1 can generate CPU interrupt requests: * Receiver overrun (OR) -- The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character
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remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. * Noise flag (NF) -- The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. Framing error (FE) -- The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. Parity error (PE) -- The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests.
*
*
16.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
16.6.1 Wait Mode The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction.
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16.6.2 Stop Mode The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. Any enabled CPU interrupt request from the SCI module does not bring the MCU out of Stop mode. SCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data.
16.7 SCI During Break Module Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See Break Module on page 171). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
16.8 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins are: * * PTE0/TxD -- Transmit data PTE1/RxD -- Receive data
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Serial Communications Interface (SCI) I/O Registers
16.8.1 PTE0/TxD (Transmit Data) The PTE0/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTE0/TxD pin with port E. When the SCI is enabled, the PTE0/TxD pin is an output regardless of the state of the DDRE2 bit in data direction register E (DDRE).
16.8.2 PTE1/RxD (Receive Data) The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE).
16.9 I/O Registers
The following I/O registers control and monitor SCI operation: * * * * * * * SCI control register 1 (SCC1) SCI control register 2 (SCC2) SCI control register 3 (SCC3) SCI status register 1 (SCS1) SCI status register 2 (SCS2) SCI data register (SCDR) SCI baud rate register (SCBR)
16.9.1 SCI Control Register 1 SCI control register 1: * * * * *
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI)
Enables loop mode operation Enables the SCI Controls output polarity Controls character length Controls SCI wakeup method
Advance Information 231
Serial Communications Interface (SCI)
* * *
Address:
Controls idle character detection Enables parity function Controls parity type
$0013 Bit 7 6 ENSCI 0 5 TXINV 0 4 M 0 3 WAKE 0 2 ILLTY 0 1 PEN 0 Bit 0 PTY 0
Read: LOOPS Write: Reset: 0
Figure 16-11. SCI Control Register 1 (SCC1) LOOPS -- Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled ENSCI -- Enable SCI Bit This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = SCI enabled 0 = SCI disabled TXINV -- Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted
NOTE:
Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits.
Advance Information 232 Serial Communications Interface (SCI)
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Serial Communications Interface (SCI) I/O Registers
M -- Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 16-8).The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE -- Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY -- Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN -- Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 16-8). When enabled, the parity function inserts a parity bit in the most significant bit position. (See Table 16-7). Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
PTY -- Parity Bit This read/write bit determines whether the SCI generates and checks for odd parity or even parity. (See Table 16-8). Reset clears the PTY bit. 1 = Odd parity 0 = Even parity
NOTE:
Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 16-8. Character Format Selection
Control Bits M 0 1 0 0 1 1 PEN:PTY 0X 0X 10 11 10 11 Start Bits 1 1 1 1 1 1 Data Bits 8 9 7 7 8 8 Character Format Parity None None Even Odd Even Odd Stop Bits 1 1 1 1 1 1 Character Length 10 Bits 11 Bits 10 Bits 10 Bits 11 Bits 11 Bits
16.9.2 SCI Control Register 2 SCI control register 2: * Enables the following CPU interrupt requests: - Enables the SCTE bit to generate transmitter CPU interrupt requests - Enables the TC bit to generate transmitter CPU interrupt requests - Enables the SCRF bit to generate receiver CPU interrupt requests - Enables the IDLE bit to generate receiver CPU interrupt requests
Advance Information 234 Serial Communications Interface (SCI)
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Serial Communications Interface (SCI) I/O Registers
* * * *
Address:
Enables the transmitter Enables the receiver Enables SCI wakeup Transmits SCI break characters
$0014 Bit 7 6 TCIE 0 5 SCRIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0
Read: SCTIE Write: Reset: 0
Figure 16-12. SCI Control Register 2 (SCC2) SCTIE -- SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE -- Transmission Complete Interrupt Enable Bit This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests SCRIE -- SCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI)
Advance Information 235
Serial Communications Interface (SCI)
ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests TE -- Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled
NOTE:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RE -- Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled
NOTE:
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RWU -- Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation
Advance Information 236 Serial Communications Interface (SCI)
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Serial Communications Interface (SCI) I/O Registers
SBK -- Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted
NOTE:
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble.
16.9.3 SCI Control Register 3 SCI control register 3: * * Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted. Enables the following interrupts: - Receiver overrun interrupts - Noise error interrupts - Framing error interrupts - Parity error interrupts
Address: $0015 Bit 7 Read: Write: Reset: U U 0 0 R 0 = Reserved 0 0 U = Unaffected 0 R8 T8 R R ORIE NEIE FEIE PEIE 6 5 4 3 2 1 Bit 0
= Unimplemented
Figure 16-13. SCI Control Register 3 (SCC3)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
R8 -- Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 -- Transmitted Bit 8 When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit. ORIE -- Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled NEIE -- Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE -- Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled PEIE -- Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled
Advance Information 238 Serial Communications Interface (SCI)
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Serial Communications Interface (SCI) I/O Registers
16.9.4 SCI Status Register 1 SCI status register 1 contains flags to signal the following conditions: * * * * * * * *
Address:
Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error Parity error
$0016 Bit 7 6 TC 5 SCRF 4 IDLE 3 OR 2 NF 1 FE Bit 0 PE
Read: Write: Reset:
SCTE
1
1
0
0
0
0
0
0
= Unimplemented
Figure 16-14. SCI Status Register 1 (SCS1) SCTE -- SCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI)
Advance Information 239
Serial Communications Interface (SCI)
TC -- Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is cleared automatically when data, preamble, or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF -- SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set the SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE -- Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared) OR -- Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE
Advance Information 240 Serial Communications Interface (SCI) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Serial Communications Interface (SCI) I/O Registers
bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 16-15 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register.
NORMAL FLAG CLEARING SEQUENCE SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 3
BYTE 1 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 2
BYTE 3
DELAYED FLAG CLEARING SEQUENCE SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 SCRF = 0 OR = 0
BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1
BYTE 3
Figure 16-15. Flag Clearing Sequence
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI)
Advance Information 241
Serial Communications Interface (SCI)
NF -- Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE -- Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE -- Receiver Parity Error Bit This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected
Advance Information 242 Serial Communications Interface (SCI)
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Serial Communications Interface (SCI) I/O Registers
16.9.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: * *
Address:
Break character detected Incoming data
$0017 Bit 7 6 0 5 0 4 0 3 0 2 0 1 BKF Bit 0 RPF
Read: Write: Reset:
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-16. SCI Status Register 2 (SCS2) BKF -- Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Serial Communications Interface (SCI)
Advance Information 243
Serial Communications Interface (SCI)
RPF -- Reception in Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress
16.9.6 SCI Data Register The SCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register.
Address: $0018 Bit 7 Read: Write: Reset: R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0
Unaffected by Reset
Figure 16-17. SCI Data Register (SCDR) R7/T7:R0/T0 -- Receive/Transmit Data Bits Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.
NOTE:
Do not use read-modify-write instructions on the SCI data register.
Advance Information 244 Serial Communications Interface (SCI)
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Serial Communications Interface (SCI) I/O Registers
16.9.7 SCI Baud Rate Register The baud rate register selects the baud rate for both the receiver and the transmitter.
Address: $0019 Bit 7 Read: Write: Reset: 0 0 0 0 R 0 = Reserved 0 0 0 0 6 0 SCP1 SCP0 R SCR2 SCR1 SCR0 5 4 3 2 1 Bit 0
= Unimplemented
Figure 16-18. SCI Baud Rate Register (SCBR) SCP1 and SCP0 -- SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 16-9. Reset clears SCP1 and SCP0. Table 16-9. SCI Baud Rate Prescaling
SCP[1:0] 00 01 10 11 Prescaler Divisor (PD) 1 3 4 13
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Serial Communications Interface (SCI)
SCR2 - SCR0 -- SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 16-10. Reset clears SCR2-SCR0. Table 16-10. SCI Baud Rate Selection
SCR[2:1:0] 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128
Use the following formula to calculate the SCI baud rate: f Crystal Baud rate = ----------------------------------64 x PD x BD where: fCrystal = crystal frequency PD = prescaler divisor BD = baud rate divisor Table 16-11 shows the SCI baud rates that can be generated with a 4.9152-MHz crystal.
Advance Information 246 Serial Communications Interface (SCI)
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Serial Communications Interface (SCI) I/O Registers
Table 16-11. SCI Baud Rate Selection Examples
SCP[1:0] 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Prescaler Divisor (PD) 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 SCR[2:1:0] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 Baud Rate (fCrystal = 4.9152 MHz) 76,800 38,400 19,200 9600 4800 2400 1200 600 25,600 12,800 6400 3200 1600 800 400 200 19,200 9600 4800 2400 1200 600 300 150 5908 2954 1477 739 369 185 92 46
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Serial Communications Interface (SCI)
Advance Information 248 Serial Communications Interface (SCI)
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Advance Information -- MC68HC08AZ60A
Section 17. Serial Peripheral Interface (SPI)
17.1 Contents
17.2 17.3 17.4 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Pin Name Conventions and I/O Register Addresses. . . . . 251
17.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 17.5.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 17.5.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 17.6 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 17.6.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . 256 17.6.2 Transmission Format When CPHA = `0'. . . . . . . . . . . . . 257 17.6.3 Transmission Format When CPHA = `1'. . . . . . . . . . . . . 258 17.6.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . 259 17.6.5 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.6.6 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 17.6.7 Mode Fault Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 17.7 17.8 17.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . 266 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268
17.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 17.10.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 17.10.2 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 17.11 SPI During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 269 17.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 17.12.1 MISO (MasterIn/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . 271 17.12.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . 271
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Serial Peripheral Interface (SPI)
17.12.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17.12.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 17.12.5 VSS (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 17.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 17.13.1 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . .274 17.13.2 SPI Status and Control Register (SPSCR) . . . . . . . . . . . 276 17.13.3 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . 280
17.2 Introduction
This section describes the serial peripheral interface module (SPI), which allows full-duplex, synchronous, serial communications with peripheral devices.
17.3 Features
Features of the SPI module include the following: * * * * * * * Full-duplex operation Master and slave modes Double-buffered operation with separate transmit and receive registers Four master mode frequencies (maximum = bus frequency / 2) Maximum slave mode frequency = bus frequency Serial clock with programmable polarity and phase Two separately enabled interrupts with CPU service: - SPRF (SPI receiver full) - SPTE (SPI transmitter empty) * * * *
Advance Information 250 Serial Peripheral Interface (SPI)
Mode fault error flag with CPU interrupt capability Overflow error flag with CPU interrupt capability Programmable wired-OR mode I2C (inter-integrated circuit) compatibility
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Serial Peripheral Interface (SPI) Pin Name Conventions and I/O Register Addresses
17.4 Pin Name Conventions and I/O Register Addresses
The generic names of the SPI input/output (I/O) pins are: * * * * SS (slave select) SPSCK (SPI serial clock) MOSI (master out slave in) MISO (master in slave out)
The SPI shares four I/O pins with a parallel I/O port. The full name of an SPI pin reflects the name of the shared port pin. Table 17-1 shows the full names of the SPI I/O pins. The generic pin names appear in the text that follows.: Table 17-1. Pin Name Conventions
SPI Generic Pin Names: Full SPI Pin Names: SPI MISO PTE5/MISO MOSI PTE6/MOSI SS PTE4/SS SCK PTE7/SPSCK VSS CGND
Table 17-2. I/O Register Addresses
Register name SPI Control Register (SPICR) SPI Status and Control Register (SPISCR) SPI Data Register (SPIDR) Register address $0010 $0011 $0012
The generic pins names appear in the text that follows.
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Advance Information 251
Serial Peripheral Interface (SPI) 17.5 Functional Description
Figure 17-1 summarizes the SPI I/O registers and Figure 17-2 show the structure of the SPI module.
Register name SPI Control Register (SPCR) Write: Reset: 0 0 1 OVRF 0 MODF 1 SPTE MODFEN SPR1 SPR0 0 R5 T5 0 R4 T4 1 R3 T3 0 R2 T2 0 R1 T1 0 R0 T0 0 0 0 R/W Read: SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Bit 7 6 5 4 3 2 1 Bit 0
SPI Status and Control Register Read: SPRF ERRIE (SPSCR) Write: Reset: Read: SPI Data Register (SPDR) Write: Reset: R T7 T6 0 R7 0 R6
Unaffected by reset = Reserved = Unimplemented
Figure 17-1. SPI I/O Register Summary
Advance Information 252 Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI) Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER
BUS CLOCK 7 6
SHIFT REGISTER 5 4 3 2 1 0 MISO
CLOCK DIVIDER
/2 /8 / 32 / 128
CLOCK SELECT
MOSI RECEIVE DATA REGISTER PIN CONTROL LOGIC SPSCK CLOCK LOGIC M S SS
SPMSTR
SPE
SPR1
SPR0
SPMSTR
CPHA
CPOL
MODFEN TRANSMITTER CPU INTERRUPT REQUEST SPI CONTROL RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE SPTIE SPRIE
SPWOM
SPE SPRF SPTE OVRF MODF
Figure 17-2. SPI Module Block Diagram The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interruptdriven. All SPI interrupts can be serviced by the CPU. The following paragraphs describe the operation of the SPI module.
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17.5.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
NOTE:
Configure the SPI modules as master and slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See SPI Control Register (SPCR) on page 274. Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI pin under the control of the serial clock. See Figure 17-3. The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. See SPI Status and Control Register (SPSCR). Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master's MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with
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Serial Peripheral Interface (SPI) Functional Description
SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTIE bit.
MASTER MCU
SLAVE MCU
SHIFT REGISTER
MISO
MISO
MOSI
MOSI
SHIFT REGISTER
SPSCK BAUD RATE GENERATOR
SPSCK
SS
VDD
SS
Figure 17-3. Full-duplex Master-Slave Connections 17.5.2 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave MCU must be at logic `0'. SS must remain low until the transmission is complete. See Mode Fault Error. In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software must then read the SPI data register before another byte enters the shift register. The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any particular SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the
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frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed. When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise the byte already in the slave shift register shifts out on the MISO pin. Data written to the slave shift register during a a transmission remains in a buffer until the end of the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. See Transmission Formats on page 256. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission.
NOTE:
SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge.
17.6 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes shifting and sampling on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate a multiple-master bus contention.
17.6.1 Clock Phase and Polarity Controls Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format.
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Serial Peripheral Interface (SPI) Transmission Formats
The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
NOTE:
Before writing to the CPOL bit or the CPHA bit, the SPI should be disabled by clearing the SPI enable bit (SPE).
17.6.2 Transmission Format When CPHA = `0' Figure 17-4 shows an SPI transmission in which CPHA is `0'. The figure should not be used as a replacement for data sheet parametric information.Two waveforms are shown for SCK: one for CPOL = `0' and another for CPOL = `1'. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic `0', so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general purpose I/O not affecting the SPI. See Mode Fault Error. When CPHA = `0', the first SPSCK edge is the MSB capture strobe. Therefore the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low again between each byte transmitted.
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SCK CYCLE # (FOR REFERENCE) SCK (CPOL ='0')
1
2
3
4
5
6
7
8
SCK (CPOL =1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) CAPTURE STROBE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
Figure 17-4. Transmission Format (CPHA = `0')
17.6.3 Transmission Format When CPHA = `1' Figure 17-5 shows an SPI transmission in which CPHA is `1'. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for CPOL = `0' and another for CPOL = `1'. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic `0', so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. See Mode Fault Error. When CPHA = `1', the master begins driving its MOSI pin on the first SPSCK edge. Therefore the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line. Figure 17-5. Transmission Format (CPHA = `1')
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Serial Peripheral Interface (SPI) Transmission Formats
SCK CYCLE # (FOR REFERENCE) SCK (CPOL ='0')
1
2
3
4
5
6
7
8
SCK (CPOL =1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) CAPTURE STROBE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
17.6.4 Transmission Initiation Latency When the SPI is configured as a master (SPMSTR = `1'), transmissions are started by a software write to the SPDR. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SCK signal. When CPHA = `0', the SCK signal remains inactive for the first half of the first SCK cycle. When CPHA = `1', the first SCK cycle begins with an edge on the SCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. See Figure 17-6. The internal SPI clock in the master is a free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits are set to conserve power. SCK edges occur halfway through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative to the slower SCK. This uncertainty causes the variation in the initiation delay shown in Figure 17-6. This delay will be no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
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WRITE TO SPDR BUS CLOCK MOSI SCK (CPHA = `1') SCK (CPHA ='0') SCK CYCLE NUMBER
INITIATION DELAY
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE TO SPDR BUS CLOCK EARLIEST LATEST
WRITE TO SPDR

BUS CLOCK BUS CLOCK BUS CLOCK
EARLIEST
WRITE TO SPDR
EARLIEST
WRITE TO SPDR
EARLIEST
Figure 17-6. Transmission Start Delay (Master)
(SCK = INTERNAL CLOCK / 2; 2 POSSIBLE START POINTS) (SCK = INTERNAL CLOCK / 8; 8 POSSIBLE START POINTS) LATEST (SCK = INTERNAL CLOCK / 32; 32 POSSIBLE START POINTS) LATEST (SCK = INTERNAL CLOCK / 128; 128 POSSIBLE START POINTS) LATEST
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Serial Peripheral Interface (SPI) Transmission Formats
17.6.5 Error Conditions The following flags signal SPI error conditions: * Overflow (OVRF) -- failing to read the SPI data register before the next byte enters the shift register results in the OVRF bit becoming set. The new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and control register. Mode fault error (MODF) -- the MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
*
17.6.6 Overflow Error The overflow flag (OVRF) becomes set if the SPI receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. See Figure 17-4 and Figure 17-5. If an overflow occurs, the data being received is not transferred to the receive data register so that the unread data can still be read. Therefore, an overflow error always indicates the loss of data. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. MODF and OVRF can generate a receiver/error CPU interrupt request. See Figure 17-9. It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is enabled to generate an interrupt, it can pull the MCU out of wait mode instead. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 17-7 shows how it is possible to miss an overflow.
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BYTE 1 1
BYTE 2 4
BYTE 3 6
BYTE 4 8
SPRF
OVRF 2 5
READ SPSCR
READ SPDR 1 2 3 4
3 5 6 7 8
7
BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT.
CPU READS SPSCRW WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 17-7. Missed Read of Overflow Condition The first part of Figure 17-7 shows how to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF flag can be set in the interval between SPSCR and SPDR being read. In this case, an overflow can easily be missed. Since no more SPRF interrupts can be generated until this OVRF is serviced, it will not be obvious that bytes are being lost as more transmissions are completed. To prevent this, the OVRF interrupt should be enabled, or alternatively another read of the SPSCR should be carried out following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions will terminate with an SPRF interrupt. Figure 17-8 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
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Serial Peripheral Interface (SPI) Transmission Formats
BYTE 1 SPI RECEIVE COMPLETE SPRF 1
BYTE 2 5
BYTE 3 7
BYTE 4 11
OVRF 2 4 6 9 8 8 9 12 14
READ SPSCR
READ SPDR 1 2 3 4 5 6 7
3 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. BYTE 2 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
10
13
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
Figure 17-8. Clearing SPRF When OVRF Interrupt is Not Enabled
17.6.7 Mode Fault Error For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared. MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and OVRF can generate a receiver/error CPU interrupt request. See Figure 17-9. It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set.
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In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic `0'. A mode fault in a master SPI causes the following events to occur: * * * * * If ERRIE = `1', the SPI generates an SPI receiver/error CPU interrupt request. The SPE bit is cleared. The SPTE bit is set. The SPI state counter is cleared. The data direction register of the shared I/O port regains control of port drivers.
NOTE:
To prevent bus contention with another master SPI after a mode fault error, clear all data direction register (DDR) bits associated with the SPI shared port pins. Setting the MODF flag (SPSCR) does not clear the SPMSTR bit. Reading SPMSTR when MODF = 1 will indicate a MODE fault error occurred in either master mode or slave mode. When configured as a slave (SPMSTR = `0'), the MODF flag is set if SS goes high during a transmission. When CPHA = `0', a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit. When CPHA = `1', the transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its IDLE level following the shift of the last data bit. See Transmission Formats.
NOTE:
NOTE:
When CPHA = `0', a MODF occurs if a slave is selected (SS is at logic `0') and later deselected (SS is at logic `1') even if no SPSCK is sent to that slave. This happens because SS at logic `0' indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = `0'. When CPHA = `1', a slave can be selected and then later deselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = `0'), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
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Serial Peripheral Interface (SPI) Interrupts
bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by toggling the SPE bit of the slave.
NOTE:
A logic `1' on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if a transmission has begun. To clear the MODF flag, read the SPSCR and then write to the SPCR register. This entire clearing procedure must occur with no MODF condition existing or else the flag will not be cleared.
17.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests: Table 17-3. SPI Interrupts
Flag SPTE (Transmitter Empty) SPRF (Receiver Full) OVRF (Overflow) MODF (Mode Fault) Request SPI Transmitter CPU Interrupt Request (SPTIE = 1) SPI Receiver CPU Interrupt Request (SPRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = `1')
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests. The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt requests, provided that the SPI is enabled (SPE = 1). The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF flag is enabled to generate receiver/error CPU interrupt requests.
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SPTE
SPTIE
SPE SPI TRANSMITTER CPU INTERRUPT REQUEST
SPRIE
SPRF
SPI RECEIVER/ERROR CPU INTERRUPT REQUEST ERRIE MODF OVRF
Figure 17-9. SPI Interrupt Request Generation Two sources in the SPI status and control register can generate CPU interrupt requests: * SPI receiver full bit (SPRF) -- the SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF can generate an SPI receiver/error CPU interrupt request. SPI transmitter empty (SPTE) -- the SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE can generate an SPTE CPU interrupt request.
*
17.8 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the SPI data register only when the SPTE bit is high. Figure 17-10 shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0).
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Serial Peripheral Interface (SPI) Queuing Transmission Data
WRITE TO SPDR
1
3
8
SPTE
2
5
10
SCK (CPHA:CPOL =`1':0) MOSI
MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 6 5 4 3 2 1 6 5 4 3 2 6 5 4 1
BYTE 1 SPRF 4
BYTE 2 9
BYTE 3
READ SPSCR
6
11
READ SPDR 1 2 3 4 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. CPU READS SPSCR WITH SPRF BIT SET. 7 8 9
7 CPU READS SPDR, CLEARING SPRF BIT.
12
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT.
10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT.
5 6
Figure 17-10. SPRF/SPTE CPU Interrupt Timing For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having to time the write of its data between the transmissions. Also, if no new data is written to the data buffer, the last value contained in the shift register will be the next data word transmitted.
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Serial Peripheral Interface (SPI) 17.9 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: * * * * * The SPTE flag is set Any transmission currently in progress is aborted The shift register is cleared The SPI state counter is cleared, making it ready for a new complete transmission All the SPI port logic is defaulted back to being general purpose I/O.
The following items are reset only by a system reset: * * * All control bits in the SPCR register All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing `0' to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
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Serial Peripheral Interface (SPI) Low-Power Modes
17.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
17.10.1 WAIT Mode The SPI module remains active after the execution of a WAIT instruction. In WAIT mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of WAIT mode. If SPI module functions are not required during WAIT mode, power consumption can be reduced by disabling the SPI module before executing the WAIT instruction. To exit WAIT mode when an overflow condition occurs, the OVRF bit should be enabled to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). See Interrupts.
17.10.2 STOP Mode The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If STOP mode is exited by reset, any transfer in progress is aborted, and the SPI is reset.
17.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM Break Flag Control Register (SBFCR). To allow software to clear status bits during a break interrupt, a `1' should be written to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.
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Serial Peripheral Interface (SPI)
To protect status bits during the break state, a `0' should be written to the BCFE bit. With BCFE at `0' (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is a `0'. After the break, the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the data register in break mode will not initiate a transmission, nor will this data be transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
17.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. * * * * * MISO -- data received MOSI -- data transmitted SPSCK -- serial clock SS -- slave select VSS -- clock ground
The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD.
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Serial Peripheral Interface (SPI) I/O Signals
17.12.1 MISO (MasterIn/Slave Out) MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic `0' and its SS pin is at locic `0'. To support a multipleslave system, a logic `1' on the SS pin puts the MISO pin in a highimpedance state. When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port.
17.12.2 MOSI (Master Out/Slave In) MOSI is one of the two SPI module pins that transmits serial data. In full duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port.
17.12.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port.
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17.12.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = `0', the SS is used to define the start of a transmission. See Transmission Formats. Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = `0' format. However, it can remain low throughout the transmission for the CPHA = `1' format. See Figure 1711.
MISO/MOSI MASTER SS SLAVE SS (CPHA ='0') SLAVE SS (CPHA = `1')
BYTE 1
BYTE 2
BYTE 3
Figure 17-11. CPHA/SS Timing When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. See SPI Status and Control Register (SPSCR).
NOTE:
A logic `1' on the SS pin of a slave SPI puts the MISO pin in a highimpedance state. The slave SPI ignores all incoming SPSCK clocks, even if transmission has already begun. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. See Mode Fault Error. For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general purpose I/O under the control of the data direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI
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Serial Peripheral Interface (SPI) I/O Registers
regardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the data register. See Table 174. Table 17-4. SPI Configuration
SPE 0 1 1 1 X = don't care SPMSTR MODFEN SPI CONFIGURATION X 0 1 1 X X 0 1 Not Enabled Slave Master without MODF Master with MODF STATE OF SS LOGIC General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI
17.12.5 VSS (Clock Ground) VSS is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin of the slave to the VSS pin.
17.13 I/O Registers
Three registers control and monitor SPI operation: * * * SPI control register (SPCR) SPI status and control register (SPSCR) SPI data register (SPDR)
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17.13.1 SPI Control Register (SPCR) The SPI control register does the following: * * * * * * Enables SPI module interrupt requests Selects CPU interrupt requests Configures the SPI module as master or slave Selects serial clock polarity and phase Configures the SPSCK, MOSI, and MISO pins as open-drain outputs Enables the SPI module
6 5 4 3 2 1 Bit 0
Bit 7 SPCR Read:
SPRIE
Write: Reset: 0 R
R
0
SPMSTR
1
CPOL
0
CPHA
1
SPWOM
0
SPE
0
SPTIE
0
= Reserved
Figure 17-12. SPI Control Register (SPCR) SPRIE -- SPI Receiver Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled SPMSTR -- SPI Master This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode
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Serial Peripheral Interface (SPI) I/O Registers
CPOL -- Clock Polarity This read/write bit determines the logic state of the SPSCK pin between transmissions. See Figure 17-4 and Figure 17-5. To transmit data between SPI modules, the SPI modules must have identical CPOL bits. Reset clears the CPOL bit. CPHA -- Clock Phase This read/write bit controls the timing relationship between the serial clock and SPI data. See Figure 17-4 and Figure 17-5. To transmit data between SPI modules, the SPI modules must have identical CPHA bits. When CPHA = `0', the SS pin of the slave SPI module must be set to logic one between bytes. See Figure 17-11. Reset sets the CPHA bit. When CPHA ='0' for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the data register. Therefore, the slave data register must be loaded with the desired transmit data before the falling edge of SS. Any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. When CPHA = `1' for a slave, the first edge of the SPSCK indicates the beginning of the transmission. The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. See Mode Fault Error. A logic `1' on the SS pin does not affect the state of the SPI state machine in any way. SPWOM -- SPI Wired-OR Mode This read/write bit disables the pull-up devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins
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SPE -- SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See Resetting the SPI. Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE-- SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled
17.13.2 SPI Status and Control Register (SPSCR) The SPI status and control register contains flags to signal the following conditions: * * * * Receive data register full Failure to clear SPRF bit before next byte is received (overflow error) Inconsistent logic level on SS pin (mode fault error) Transmit data register empty
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Serial Peripheral Interface (SPI) I/O Registers
The SPI status and control register also contains bits that perform the following functions: * * * Enable error interrupts Enable mode fault error detection Select master SPI baud rate
Bit 7 SPSCR Read: Write: Reset: 0 R 0 = Reserved 0 0 1 6 5 4 3 2 1 Bit 0
SPRF ERRIE
OVRF
MODF
SPTE
MODFE N
0
SPR1
0
SPR0
0
= Unimplemented
Figure 17-13. SPI Status and Control Register (SPSCR) SPRF -- SPI Receiver Full This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Any read of the SPI data register clears the SPRF bit. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full ERRIE -- Error Interrupt Enable This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF -- Overflow Flag This clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. In an overflow condition, the byte already in the receive data
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register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the SPI data register. Reset clears the OVRF flag. 1 = Overflow 0 = No overflow MODF -- Mode Fault This clearable, ready-only flag is set in a slave SPI if the SS pin goes high during a transmission. In a master SPI, the MODF flag is set if the SS pin goes low at any time. Clear the MODF bit by reading the SPI status and control register with MODF set and then writing to the SPI data register. Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE -- SPI Transmitter Empty This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request if the SPTIE bit in the SPI control register is set also.
NOTE:
The SPI data register should not be written to unless the SPTE bit is high. For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE will be set again within two bus cycles since the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty
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Serial Peripheral Interface (SPI) I/O Registers
MODFEN -- Mode Fault Enable This read/write bit, when set to `1', allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general purpose I/O. If the MODFEN bit is set, then this pin is not available as a general purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general purpose I/O regardless of the value of MODFEN. See SS (Slave Select). If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. See Mode Fault Error. SPR1 and SPR0 -- SPI Baud Rate Select In master mode, these read/write bits select one of four baud rates as shown in Table 17-5. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 17-5. SPI Master Baud Rate Selection
SPR1:SPR0 00 01 10 11 Baud rate divisor (BD) 2 8 32 128
The following formula is used to calculate the SPI baud rate:
CGMOUT Baud rate = --------------------------2 x BD
where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor
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17.13.3 SPI Data Register (SPDR) The SPI data register is the read/write buffer for the receive data register and the transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate buffers that can contain different values. See Figure 17-2.
Bit 7 SPDR Read: Write: Reset: 6 5 4 3 2 1 Bit 0
R7 T7
R6 T6
R5 T5
R4 T4
R3 T3
R2 T2
R1 T1
R0 T0
Indeterminate after reset
Figure 17-14. SPI Data Register (SPDR) R7:R0/T7:T0 -- Receive/Transmit Data Bits
NOTE:
Do not use Read-modify-write instructions on the SPI data register since the buffer read is not the same as the buffer written.
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Section 18. Timer Interface Module B (TIMB)
18.1 Contents
18.2 18.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
18.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 18.4.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . 284 18.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 18.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 18.4.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . 286 18.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . .287 18.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . .288 18.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . 289 18.4.4.2 Buffered PWM Signal Generation. . . . . . . . . . . . . . . . 290 18.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 18.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
18.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 18.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 18.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 18.7 TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 293
18.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 18.8.1 TIMB Clock Pin (PTD4/ATD12/TBCLK) . . . . . . . . . . . . . . 293 18.8.2 TIMB Channel I/O Pins (PTF5/TBCH1-PTF4/TBCH0) . . 294 18.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 18.9.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . . 295 18.9.2 TIMB Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . 297 18.9.3 TIMB Counter Modulo Registers. . . . . . . . . . . . . . . . . . . 298 18.9.4 TIMB Channel Status and Control Registers. . . . . . . . . 299 18.9.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . 303
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Timer Interface Module B (TIMB) 18.2 Introduction
This section describes the timer interface module (TIMB). The TIMB is a 2-channel timer that provides a timing reference with input capture, output compare and pulse width modulation functions. Figure 18-1 is a block diagram of the TIMB. For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer Reference Manual, TIM08RM/AD.
18.3 Features
Features of the TIMB include: * Two Input Capture/Output Compare Channels - Rising-Edge, Falling-Edge or Any-Edge Input Capture Trigger - Set, Clear or Toggle Output Compare Action * * Buffered and Unbuffered Pulse Width Modulation (PWM) Signal Generation Programmable TIMB Clock Input - 7 Frequency Internal Bus Clock Prescaler Selection - External TIMB Clock Input (4 MHz Maximum Frequency) * * * Free-Running or Modulo Up-Count Operation Toggle Any Channel Pin on Overflow TIMB Counter Stop and Reset Bits
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Timer Interface Module B (TIMB) Features
PTD4/ATD12/TBCLK INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER
TCLK PRESCALER SELECT PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F ELS1B ELS1A MS0B CH0IE TOV1 CH1MAX CH0F ELS0B ELS0A TOV0 CH0MAX
PTF4 LOGIC INTERRUPT LOGIC
PTF4/TBCH0
PTF5 LOGIC INTERRUPT LOGIC
PTF5/TBCH1
Figure 18-1. TIMB Block Diagram Figure 18-2. TIMB I/O Register Summary
Addr. $0040 $0041 $0042 $0043 $0044 $0045 $0046 Register Name TIMB Status/Control Register (TBSC) TIMB Counter Register High (TBCNTH) TIMB Counter Register Low (TBCNTL)
R: W: R: W: R: W:
Bit 7 TOF 0 Bit 15 R Bit 7 R Bit 15 Bit 7 CH0F 0 Bit 15
6 TOIE 14 R 6 R 14 6 CH0IE 14
5 TSTOP 13 R 5 R 13 5 MS0B 13
4 0 TRST 12 R 4 R 12 4 MS0A 12
3 0 R 11 R 3 R 11 3 ELS0B 11
2 PS2 10 R 2 R 10 2 ELS0A 10
1 PS1 9 R 1 R 9 1 TOV0 9
Bit 0 PS0 Bit 8 R Bit 0 R Bit 8 Bit 0 CH0MAX Bit 8
TIMB Counter Modulo Reg. High R: (TBMODH) W: TIMB Counter Modulo Reg. Low R: (TBMODL) W: TIMB Ch. 0 Status/Control Register R: (TBSC0) W: TIMB Ch. 0 Register High (TBCH0H)
R: W:
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Figure 18-2. TIMB I/O Register Summary
Addr. $0047 $0048 $0049 $004A Register Name TIMB Ch. 0 Register Low (TBCH0L)
R: W:
Bit 7 Bit 7 CH1F 0 Bit 15 Bit 7
6 6 CH1IE 14 6
5 5 0 R 13 5
4 4 MS1A 12 4
3 3 ELS1B 11 3
2 2 ELS1A 10 2
1 1 TOV1 9 1
Bit 0 Bit 0 CH1MAX Bit 8 Bit 0
TIMB Ch. 1 Status/Control Register R: (TBSC1) W: TIMB Ch. 1 Register High (TBCH1H) TIMB Ch. 1 Register Low (TBCH1L)
R: W: R: W:
R
= Reserved
18.4 Functional Description
Figure 18-1 shows the TIMB structure. The central component of the TIMB is the 16-bit TIMB counter that can operate as a free-running counter or a modulo up-counter. The TIMB counter provides the timing reference for the input capture and output compare functions. The TIMB counter modulo registers, TBMODH-TBMODL, control the modulo value of the TIMB counter. Software can read the TIMB counter value at any time without affecting the counting sequence. The two TIMB channels are programmable independently as input capture or output compare channels.
18.4.1 TIMB Counter Prescaler The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin, PTD4/ATD12/TBCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMB status and control register select the TIMB clock source.
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Timer Interface Module B (TIMB) Functional Description
18.4.2 Input Capture An input capture function has three basic parts: edge select logic, an input capture latch and a 16-bit counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The polarity of the active edge is programmable. The level transition which triggers the counter transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0 through TBSC1 control registers with x referring to the active channel number). When an active edge occurs on the pin of an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel registers, TBCHxH-TBCHxL. Input captures can generate TIMB CPU interrupt requests. Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. The free-running counter contents are transferred to the TIMB channel register (TBCHxH-TBCHxL, see TIMB Channel Registers on page 303) on each proper signal transition regardless of whether the TIMB channel flag (CH0F-CH1F in TBSC0-TBSC1 registers) is set or clear. When the status flag is set, a CPU interrupt is generated if enabled. The value of the count latched or "captured" is the time of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. However, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. By recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the overflows at the 16-bit module counter to extend its range. Another use for the input capture function is to establish a time reference. In this case, an input capture function is used in conjunction with an output compare function. For example, to activate an output signal a specified number of clock cycles after detecting an input event
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(edge), use the input capture function to record the time at which the edge occurred. A number corresponding to the desired delay is added to this captured value and stored to an output compare register (see TIMB Channel Registers on page 303). Because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. Reset does not affect the contents of the input capture channel register (TBCHxH-TBCHxL).
18.4.3 Output Compare With the output compare function, the TIMB can generate a periodic pulse with a programmable polarity, duration and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMB can set, clear or toggle the channel pin. Output compares can generate TIMB CPU interrupt requests. 18.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in Output Compare on page 286. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMB channel registers. An unsynchronized write to the TIMB channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIMB overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMB may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
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Timer Interface Module B (TIMB) Functional Description
*
When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
*
18.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTF4/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The output compare value in the TIMB channel 0 registers initially controls the output on the PTF4/TBCH0 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the output after the TIMB overflows. At each subsequent overflow, the TIMB channel registers (0 or 1) that control the output are the ones written to last. TBSC0 controls and monitors the buffered output compare function and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
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Timer Interface Module B (TIMB)
18.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIMB can generate a PWM signal. The value in the TIMB counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMB counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 18-3 shows, the output compare value in the TIMB channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMB to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMB to set the pin if the state of the PWM pulse is logic 0.
OVERFLOW PERIOD OVERFLOW OVERFLOW
PULSE WIDTH PTEx/TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 18-3. PWM Period and Pulse Width The value in the TIMB counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIMB counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000 (see TIMB Status and Control Register). The value in the TIMB channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMB channel registers produces a duty cycle of 128/256 or 50%.
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Timer Interface Module B (TIMB) Functional Description
18.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in Pulse Width Modulation (PWM) on page 288. The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIMB channel registers. An unsynchronized write to the TIMB channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIMB overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIMB may pass the new value before it is written to the TIMB channel registers. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
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18.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTF4/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers initially control the pulse width on the PTF4/TBCH0 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMB channel registers (0 or 1) that control the pulse width are the ones written to last. TBSC0 controls and monitors the buffered PWM function, and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
18.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMB status and control register (TBSC): a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP. b. Reset the TIMB counter and prescaler by setting the TIMB reset bit, TRST. 2. In the TIMB counter modulo registers (TBMODH-TBMODL) write the value for the required PWM period. 3. In the TIMB channel x registers (TBCHxH-TBCHxL) write the value for the required pulse width.
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MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Timer Interface Module B (TIMB) Functional Description
4. In TIMB channel x status and control register (TBSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB-MSxA (see Table 18-2). b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB-ELSxA. The output action on compare must force the output to the complement of the pulse width level (see Table 18-2).
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIMB status control register (TBSC) clear the TIMB stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMB channel 0 registers (TBCH0H-TBCH0L) initially control the buffered PWM output. TIMB status control register 0 (TBSC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMB overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output (see TIMB Channel Status and Control Registers on page 299).
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Timer Interface Module B (TIMB)
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Timer Interface Module B (TIMB) 18.5 Interrupts
The following TIMB sources can generate interrupt requests: * TIMB overflow flag (TOF) -- The TOF bit is set when the TIMB counter value reaches the value in the TIMB counter modulo registers. The TIMB overflow interrupt enable bit, TOIE, enables TIMB overflow CPU interrupt requests. TOF and TOIE are in the TIMB status and control register. TIMB channel flags (CH1F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIMB CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE.
*
18.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
18.6.1 Wait Mode The TIMB remains active after the execution of a WAIT instruction. In wait mode, the TIMB registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMB can bring the MCU out of wait mode. If TIMB functions are not required during wait mode, reduce power consumption by stopping the TIMB before executing the WAIT instruction.
18.6.2 Stop Mode The TIMB is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIMB counter. TIMB operation resumes when the MCU exits stop mode.
Advance Information 292 Timer Interface Module B (TIMB)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Timer Interface Module B (TIMB) TIMB During Break Interrupts
18.7 TIMB During Break Interrupts
A break interrupt stops the TIMB counter and inhibits input captures. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state (see SIM Break Flag Control Register (SBFCR) on page 137). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
18.8 I/O Signals
Port D shares one of its pins with the TIMB. Port F shares two of its pins with the TIMB. PTD4/ATD12/TBCLK is an external clock input to the TIMB prescaler. The two TIMB channel I/O pins are PTF4/TBCH0 and PTF5/TBCH1.
18.8.1 TIMB Clock Pin (PTD4/ATD12/TBCLK) PTD4/ATD12/TBCLK is an external clock input that can be the clock source for the TIMB counter instead of the prescaled internal bus clock. Select the PTD4/ATD12/TBCLK input by writing logic 1s to the three prescaler select bits, PS[2:0] (see TIMB Status and Control Register). The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 ------------------------------------ + t SU bus frequency
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Timer Interface Module B (TIMB)
The maximum TCLK frequency is the least: 4 MHz or bus frequency / 2. PTD4/ATD12/TBCLK is available as a general-purpose I/O pin or ADC channel when not used as the TIMB clock input. When the PTD4/ATD12/TBCLK pin is the TIMB clock input, it is an input regardless of the state of the DDRD4 bit in data direction register D.
18.8.2 TIMB Channel I/O Pins (PTF5/TBCH1-PTF4/TBCH0) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTF4/TBCH0 and PTF5/TBCH1 can be configured as buffered output compare or buffered PWM pins.
18.9 I/O Registers
These I/O registers control and monitor TIMB operation: * * * * * TIMB status and control register (TBSC) TIMB control registers (TBCNTH-TBCNTL) TIMB counter modulo registers (TBMODH-TBMODL) TIMB channel status and control registers (TBSC0 and TBSC1) TIMB channel registers (TBCH0H-TBCH0L, TBCH1H-TBCH1L)
Advance Information 294 Timer Interface Module B (TIMB)
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Timer Interface Module B (TIMB) I/O Registers
18.9.1 TIMB Status and Control Register The TIMB status and control register: * * * * *
Address:
Enables TIMB overflow interrupts Flags TIMB overflows Stops the TIMB counter Resets the TIMB counter Prescales the TIMB counter clock
$0040 Bit 7 6 TOIE 5 TSTOP TRST 0 = Reserved 1 0 R 0 0 0 0 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0
Read: Write: Reset:
TOF 0 0 R
Figure 18-4. TIMB Status and Control Register (TBSC) TOF -- TIMB Overflow Flag Bit This read/write flag is set when the TIMB counter reaches the modulo value programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control register when TOF is set and then writing a logic 0 to TOF. If another TIMB overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIMB counter has reached modulo value 0 = TIMB counter has not reached modulo value TOIE -- TIMB Overflow Interrupt Enable Bit This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMB overflow interrupts enabled 0 = TIMB overflow interrupts disabled
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Timer Interface Module B (TIMB)
TSTOP -- TIMB Stop Bit This read/write bit stops the TIMB counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMB counter until software clears the TSTOP bit. 1 = TIMB counter stopped 0 = TIMB counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIMB is required to exit wait mode. Also, when the TSTOP bit is set and the timer is configured for input capture operation, input captures are inhibited until TSTOP is cleared. TRST -- TIMB Reset Bit Setting this write-only bit resets the TIMB counter and the TIMB prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMB counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIMB counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIMB counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select either the PTD4/ATD12/TBCLK pin or one of the seven prescaler outputs as the input to the TIMB counter as Table 18-1 shows. Reset clears the PS[2:0] bits. Table 18-1. Prescaler Selection
PS[2:0] 000 001 010 011 100 101 110 111 TIMB Clock Source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 PTD4/ATD12/TBCLK MC68HC08AZ60A -- Rev 0.0 Timer Interface Module B (TIMB) MOTOROLA
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Timer Interface Module B (TIMB) I/O Registers
18.9.2 TIMB Counter Registers The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter. Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.
NOTE:
If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL retains the value latched during the break.
Register Name and Address TBCNTH -- $0041 Bit 7 Read: Write: Reset: BIT 15 R 0 6 BIT 14 R 0 5 BIT 13 R 0 4 BIT 12 R 0 3 BIT 11 R 0 2 BIT 10 R 0 1 BIT 9 R 0 Bit 0 BIT 8 R 0
Register Name and Address TBCNTL -- $0042 Bit 7 Read: Write: Reset: BIT 7 R 0 R 6 BIT 6 R 0 R = Reserved 5 BIT 5 R 0 4 BIT 4 R 0 3 BIT 3 R 0 2 BIT 2 R 0 1 BIT 1 R 0 Bit 0 BIT 0 R 0
Figure 18-5. TIMB Counter Registers (TBCNTH and TBCNTL)
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Timer Interface Module B (TIMB)
18.9.3 TIMB Counter Modulo Registers The read/write TIMB modulo registers contain the modulo value for the TIMB counter. When the TIMB counter reaches the modulo value, the overflow flag (TOF) becomes set and the TIMB counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TBMODH) inhibits the TOF bit and overflow interrupts until the low byte (TBMODL) is written. Reset sets the TIMB counter modulo registers.
Register Name and Address TBMODH -- $0043 Bit 7 Read: BIT 15 Write: Reset: 1 1 1 1 1 1 1 1 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 6 5 4 3 2 1 Bit 0
Register Name and Address TBMODL -- $0044 Bit 7 Read: BIT 7 Write: Reset: 1 1 1 1 1 1 1 1 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 6 5 4 3 2 1 Bit 0
Figure 18-6. TIMB Counter Modulo Registers (TBMODH and TBMODL)
NOTE:
Reset the TIMB counter before writing to the TIMB counter modulo registers.
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Timer Interface Module B (TIMB) I/O Registers
18.9.4 TIMB Channel Status and Control Registers Each of the TIMB channel status and control registers: * * * * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare or PWM operation Selects high, low or toggling output on output compare Selects rising edge, falling edge or any edge as the active input capture trigger Selects output toggling on TIMB overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
Register Name and Address TBSC0 -- $0045 Bit 7 Read: Write: Reset: CH0F CH0IE 0 0 0 0 0 0 0 0 0 MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 6 5 4 3 2 1 Bit 0
Register Name and Address TBSC1 -- $0048 Bit 7 Read: Write: Reset: CH1F CH1IE 0 0 R 0 R = Reserved R 0 0 0 0 0 0 6 5 0 MS1A ELS1B ELS1A TOV1 CH1MAX 4 3 2 1 Bit 0
Figure 18-7. TIMB Channel Status and Control Registers (TBSC0-TBSC1)
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Timer Interface Module B (TIMB)
CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIMB counter registers matches the value in the TIMB channel x registers. When CHxIE = 1, clear CHxF by reading TIMB channel x status and control register with CHxF set, and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIMB CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB channel 0. Setting MS0B disables the channel 1 status and control register and reverts TBCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled
Advance Information 300 Timer Interface Module B (TIMB)
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Timer Interface Module B (TIMB) I/O Registers
MSxA -- Mode Select Bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation (see Table 18-2). 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TBCHx pin once PWM, input capture or output compare operation is enabled (see Table 18-2). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMB status and control register (TBSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port F and pin PTFx/TBCHx is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits and becomes transparent to the respective pin when PWM, input capture, or output compare mode is enabled. Table 18-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
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Timer Interface Module B (TIMB)
Table 18-2. Mode, Edge, and Level Selection
MSxB:MSxA X0 ELSxB:ELSxA 00 Output Preset X1 00 00 00 01 01 01 1X 1X 1X 00 01 10 11 01 10 11 01 10 11 Output Compare or PWM Buffered Output Compare or Buffered PWM Input Capture Mode Configuration Pin under Port Control; Initialize Timer Output Level High Pin under Port Control; Initialize Timer Output Level Low Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare
NOTE:
Before enabling a TIMB channel register for input capture operation, make sure that the PTFx/TBCHx pin is stable for at least two bus clocks. TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMB counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMB counter overflow. 0 = Channel x pin does not toggle on TIMB counter overflow.
NOTE:
When TOVx is set, a TIMB counter overflow takes precedence over a channel x output compare if both occur at the same time.
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Timer Interface Module B (TIMB) I/O Registers
CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 18-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 18-8. CHxMAX Latency
18.9.5 TIMB Channel Registers These read/write registers contain the captured TIMB counter value of the input capture function or the output compare value of the output compare function. The state of the TIMB channel registers after reset is unknown. In input capture mode (MSxB-MSxA = 0:0) reading the high byte of the TIMB channel x registers (TBCHxH) inhibits input captures until the low byte (TBCHxL) is read. In output compare mode (MSxB-MSxA 0:0) writing to the high byte of the TIMB channel x registers (TBCHxH) inhibits output compares and the CHxF bit until the low byte (TBCHxL) is written.
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Timer Interface Module B (TIMB)
Register Name and Address TBCH0H -- $0046 Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0
Register Name and Address TBCH0L -- $0047 Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0
Register Name and Address TBCH1H -- $0049 Bit 7 Read: Bit 15 Write: Reset: Indeterminate after Reset Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0
Register Name and Address TBCH1L -- $004A Bit 7 Read: Bit 7 Write: Reset: Indeterminate after Reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 18-9. TIMB Channel Registers (TBCH0H/L-TBCH1H/L)
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Advance Information -- MC68HC08AZ60A
Section 19. Programmable Interrupt Timer (PIT)
19.1 Contents
19.2 19.3 19.4 19.5 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
19.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 19.7 PIT During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . 308
19.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 19.8.1 PIT Status and Control Register . . . . . . . . . . . . . . . . . . . 309 19.8.2 PIT Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 19.8.3 PIT Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 313
19.2 Introduction
This section describes the Programmable Interrupt Timer (PIT) which is a periodic interrupt timer whose counter is clocked internally via software programmable options. Figure 19-1 is a block diagram of the PIT. For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer Reference Manual, TIM08RM/AD.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT)
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Programmable Interrupt Timer (PIT) 19.3 Features
Features of the PIT include: * * * Programmable PIT Clock Input Free-Running or Modulo Up-Count Operation PIT Counter Stop and Reset Bits
19.4 Functional Description
Figure 19-1 shows the structure of the PIT. The central component of the PIT is the 16-bit PIT counter that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the interrupt. The PIT counter modulo registers, PMODH-PMODL, control the modulo value of the counter. Software can read the counter value at any time without affecting the counting sequence.
INTERNAL BUS CLOCK CSTOP CRST
PRESCALER SELECT PRESCALER
PPS2
PPS1
PPS0
16-BIT COUNTER 16-BIT COMPARATOR PMODH:PMODL
POF POIE
INTERRUPT LOGIC
Figure 19-1. PIT Block Diagram
Advance Information 306 Programmable Interrupt Timer (PIT)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Programmable Interrupt Timer (PIT) PIT Counter Prescaler
Register Name Read: PIT Status and Control Register Write: (PSC) Reset: Read: PIT Counter Register High Write: (PCNTH) Reset: Read: PIT Counter Register Low Write: (PCNTL) Reset: Read: PIT Counter Modulo Register High Write: (PMODH) Reset: Read: PIT Counter Modulo Register Low Write: (PMODL) Reset:
Bit 7 POF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1
6 POIE 0 14 0 6 0 14 1 6 1
5 PSTOP 1 13 0 5 0 13 1 5 1
4 0 PRST 0 12 0 4 0 12 1 4 1
3 0 0 11 0 3 0 11 1 3 1
2 PPS2 0 10 0 2 0 10 1 2 1
1 PPS1 0 9 0 1 0 9 1 1 1
Bit 0 PPS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1
=Unimplemented
Figure 19-2. PIT I/O Register Summary Table 19-1. PIT I/O Register Address Summary
Register Address PSC $004B PCNTH $004C PCNTL $004D PMODH $004E PMODL $004F
19.5 PIT Counter Prescaler
The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PPS[2:0], in the status and control register select the PIT clock source. The value in the PIT counter modulo registers and the selected prescaler output determines the frequency of the periodic interrupt. The PIT overflow flag (POF) is set when the PIT counter value reaches the
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT)
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Programmable Interrupt Timer (PIT)
modulo value programmed in the PIT counter modulo registers. The PIT interrupt enable bit, POIE, enables PIT overflow CPU interrupt requests. POF and POIE are in the PIT status and control register.
19.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
19.6.1 Wait Mode The PIT remains active after the execution of a WAIT instruction. In wait mode the PIT registers are not accessible by the CPU. Any enabled CPU interrupt request from the PIT can bring the MCU out of wait mode. If PIT functions are not required during wait mode, reduce power consumption by stopping the PIT before executing the WAIT instruction.
19.6.2 Stop Mode The PIT is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the PIT counter. PIT operation resumes when the MCU exits stop mode after an external interrupt.
19.7 PIT During Break Interrupts
A break interrupt stops the PIT counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state (see SIM Break Flag Control Register (SBFCR) on page 137).
Advance Information 308 Programmable Interrupt Timer (PIT)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Programmable Interrupt Timer (PIT) I/O Registers
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
19.8 I/O Registers
The following I/O registers control and monitor operation of the PIT: * * * PIT status and control register (PSC) PIT counter registers (PCNTH-PCNTL) PIT counter modulo registers (PMODH-PMODL)
19.8.1 PIT Status and Control Register The PIT status and control register: * * * * * Enables PIT interrupt Flags PIT overflows Stops the PIT counter Resets the PIT counter Prescales the PIT counter clock
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT)
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Programmable Interrupt Timer (PIT)
Address:
$004B Bit 7 6 POIE 5 PSTOP PRST 0 1 0 0 0 0 0 4 0 3 0 PPS2 PPS1 PPS0 2 1 Bit 0
Read: Write: Reset:
POF 0 0
= Unimplemented
Figure 19-3. PIT Status and Control Register (PSC) POF -- PIT Overflow Flag Bit This read/write flag is set when the PIT counter reaches the modulo value programmed in the PIT counter modulo registers. Clear POF by reading the PIT status and control register when POF is set and then writing a logic 0 to POF. If another PIT overflow occurs before the clearing sequence is complete, then writing logic 0 to POF has no effect. Therefore, a POF interrupt request cannot be lost due to inadvertent clearing of POF. Reset clears the POF bit. Writing a logic 1 to POF has no effect. 1 = PIT counter has reached modulo value 0 = PIT counter has not reached modulo value POIE -- PIT Overflow Interrupt Enable Bit This read/write bit enables PIT overflow interrupts when the POF bit becomes set. Reset clears the POIE bit. 1 = PIT overflow interrupts enabled 0 = PIT overflow interrupts disabled PSTOP -- PIT Stop Bit This read/write bit stops the PIT counter. Counting resumes when PSTOP is cleared. Reset sets the PSTOP bit, stopping the PIT counter until software clears the PSTOP bit. 1 = PIT counter stopped 0 = PIT counter active
Advance Information 310 Programmable Interrupt Timer (PIT)
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Programmable Interrupt Timer (PIT) I/O Registers
NOTE:
Do not set the PSTOP bit before entering wait mode if the PIT is required to exit wait mode. PRST -- PIT Reset Bit Setting this write-only bit resets the PIT counter and the PIT prescaler. Setting PRST has no effect on any other registers. Counting resumes from $0000. PRST is cleared automatically after the PIT counter is reset and always reads as logic zero. Reset clears the PRST bit. 1 = Prescaler and PIT counter cleared 0 = No effect
NOTE:
Setting the PSTOP and PRST bits simultaneously stops the PIT counter at a value of $0000. PPS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the PIT counter as Table 19-2 shows. Reset clears the PPS[2:0] bits. Table 19-2. Prescaler Selection
PPS[2:0] 000 001 010 011 100 101 110 111 PIT Clock Source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 Internal Bus Clock / 64
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Programmable Interrupt Timer (PIT)
19.8.2 PIT Counter Registers The two read-only PIT counter registers contain the high and low bytes of the value in the PIT counter. Reading the high byte (PCNTH) latches the contents of the low byte (PCNTL) into a buffer. Subsequent reads of PCNTH do not affect the latched PCNTL value until PCNTL is read. Reset clears the PIT counter registers. Setting the PIT reset bit (PRST) also clears the PIT counter registers.
NOTE:
If you read PCNTH during a break interrupt, be sure to unlatch PCNTL by reading PCNTL before exiting the break interrupt. Otherwise, PCNTL retains the value latched during the break.
Address: $004C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Address: $004D Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
= Unimplemented
Figure 19-4. PIT Counter Registers (PCNTH-PCNTL)
Advance Information 312 Programmable Interrupt Timer (PIT)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Programmable Interrupt Timer (PIT) I/O Registers
19.8.3 PIT Counter Modulo Registers The read/write PIT modulo registers contain the modulo value for the PIT counter. When the PIT counter reaches the modulo value the overflow flag (POF) becomes set and the PIT counter resumes counting from $0000 at the next timer clock. Writing to the high byte (PMODH) inhibits the POF bit and overflow interrupts until the low byte (PMODL) is written. Reset sets the PIT counter modulo registers.
Address: $004E:$004F Bit 7 Read: Bit 15 Write: Reset: 1 1 1 1 1 1 1 1 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0
Address: $004E:$004F Bit 7 Read: Bit 7 Write: Reset: 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 19-5. PIT Counter Modulo Registers (PMODH-PMODL)
NOTE:
Reset the PIT counter before writing to the PIT counter modulo registers.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Programmable Interrupt Timer (PIT)
Advance Information 313
Programmable Interrupt Timer (PIT)
Advance Information 314 Programmable Interrupt Timer (PIT)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 20. I/O Ports
20.1 Contents
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
20.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 20.3.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . 317 20.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . 318 20.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320 20.4.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . 320 20.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . 321 20.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 20.5.1 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . 323 20.5.2 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . 324 20.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 20.6.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . 326 20.6.2 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . 327 20.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 20.7.1 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . 329 20.7.2 Data Direction Register E (DDRE). . . . . . . . . . . . . . . . . . 332 20.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 20.8.1 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . 334 20.8.2 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . 335 20.9 Port G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337 20.9.1 Port G Data Register (PTG) . . . . . . . . . . . . . . . . . . . . . . . 337 20.9.2 Data Direction Register G (DDRG) . . . . . . . . . . . . . . . . . 338 20.10 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 20.10.1 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . 340 20.10.2 Data Direction Register H (DDRH) . . . . . . . . . . . . . . . . . 341
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 315
I/O Ports 20.2 Introduction
Fifty bidirectional input-output (I/O) pins form eight parallel ports. All I/O pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Table 20-1. I/O Port Register Summary
Register Name Port A Data Register (PTA) Port B Data Register (PTB) Port C Data Register (PTC) Port D Data Register (PTD) Data Direction Register A (DDRA) Data Direction Register B (DDRB) Data Direction Register C (DDRC) Data Direction Register D (DDRD) Port E Data Register (PTE) Port F Data Register (PTF) Port G Data Register (PTG) Port H Data Register (PTH) Data Direction Register E (DDRE) Data Direction Register F (DDRF) R: W: R: W: R: W: R: W: R: W: R: W:
Bit 7 PTA7 PTB7 0 PTD7
6 PTA6 PTB6 0 PTD6
5 PTA5 PTB5 PTC5 PTD5
4 PTA4 PTB4 PTC4 PTD4
3 PTA3 PTB3 PTC3 PTD3
2 PTA2 PTB2 PTC2 PTD2
1 PTA1 PTB1 PTC1 PTD1
Bit 0
Addr.
PTA0 $0000 PTB0 $0001 PTC0 $0002 PTD0 $0003
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0004 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0005 MCLKEN 0 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 $0006
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0 $0007 PTE7 0 0 0 PTE6 PTF6 0 0 PTE5 PTF5 0 0 PTE4 PTF4 0 0 PTE3 PTF3 0 0 PTE2 PTF2 PTG2 0 PTE1 PTF1 PTG1 PTH1 PTE0 $0008 PTF0 $0009 PTG0 $000A PTH0 $000B
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 $000C 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 $000D
Advance Information 316 I/O Ports
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port A
Table 20-1. I/O Port Register Summary (Continued)
Register Name Data Direction Register G (DDRG) Data Direction Register H (DDRH) R: W: R: W:
= Unimplemented
Bit 7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2
1
Bit 0
Addr.
DDRG2 DDRG1 DDRG0 $000E 0 DDRH1 DDRH0 $000F
20.3 Port A
Port A is an 8-bit general-purpose bidirectional I/O port.
20.3.1 Port A Data Register (PTA) The port A data register contains a data latch for each of the eight port A pins.
Bit 7 PTA $0000 Read: 6 5 4 3 2 1 Bit 0
PTA7
Write: Reset:
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Unaffected by reset
Figure 20-1. Port A data register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 317
I/O Ports
20.3.2 Data Direction Register A (DDRA) Data direction register A determines whether each port A pin is an input or an output. Writing a logic one to a DDRA bit enables the output buffer for the corresponding port A pin; a logic zero disables the output buffer.
Bit 7 DDRA $0004 Read: 6 5 4 3 2 1 Bit 0
DDRA7
Write: Reset: 0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
DDRA2
0
DDRA1
0
DDRA0
0
Figure 20-2 Data Direction Register A (DDRA) DDRA[7:0] -- Data direction register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 20-3 shows the port A I/O logic.
READ DDRA ($0004)
INTERNAL DATA BUS
WRITE DDRA ($0004) RESET WRITE PTA ($0000) PTAx PTAx DDRAx
READ PTA ($0000)
Figure 20-3. Port A I/O Circuit
Advance Information 318 I/O Ports
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port A
When bit DDRAx is a logic one, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic zero, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-2 summarizes the operation of the port A pins.
Table 20-2. Port A pin functions
DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTA Read Pin PTA[7:0] Write PTA[7:0](3) PTA[7:0]
X(1) X
Input, Hi-Z(2) Output
DDRA[7:0] DDRA[7:0]
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 319
I/O Ports 20.4 Port B
Port B is an 8-bit special function port that shares all of its pins with the analog to digital convertor.
20.4.1 Port B Data Register (PTB) The port B data register contains a data latch for each of the eight port B pins.
Bit 7 PTB $0001 Read: 6 5 4 3 2 1 Bit 0
PTB7
Write: Reset:
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Unaffected by reset
ALTERNATE FUNCTIONS
ATD7
ATD6
ATD5
ATD4
ATD3
ATD2
ATD1
ATD0
Figure 20-4. Port B Data Register (PTB) PTB[7:0] -- Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. ATD[7:0] -- ADC Channels
NOTE:
PTB7/ATD7- PTB0/ATD0 are eight of the analog to digital converter channels. The ADC channel select bits, CH[4:0], determine whether the PTB7/ATD7-PTB0/ATD0 pins are ADC channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be zero if the data direction for this bit is programmed as an input. Otherwise, the data will reflect the value in the data latch. Data direction register B (DDRB) does not affect the data direction of port B pins that are being used by the ADC. However, the DDRB bits always determine whether reading port B returns the states of the latches or logic 0.
Advance Information 320 I/O Ports
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port B
20.4.2 Data Direction Register B (DDRB) Data direction register B determines whether each port B pin is an input or an output. Writing a logic one to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output buffer.
Bit 7 DDRB $0005 Read: 6 5 4 3 2 1 Bit 0
DDRB7
Write: Reset: 0
DDRB6
0
DDRB5
0
DDRB4
0
DDRB3
0
DDRB2
0
DDRB1
0
DDRB0
0
Figure 20-5. Data Direction Register B (DDRB) DDRB[7:0] -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 20-6 shows the port B I/O logic.
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005) RESET WRITE PTB ($0001) PTBx PTBx DDRBx
READ PTB ($0001)
Figure 20-6. Port B I/O Circuit
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 321
I/O Ports
When bit DDRBx is a logic one, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic zero, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-3 summarizes the operation of the port B pins. Table 20-3. Port B Pin Functions
DDRB Bit PTB Bit I/O Pin Mode Accesses to DDRB Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTB Read Pin PTB[7:0] Write PTB[7:0](3) PTB[7:0]
X(1) X
Input, Hi-Z(2) Output
DDRB[7:0] DDRB[7:0]
Advance Information 322 I/O Ports
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port C
20.5 Port C
Port C is a 6-bit general-purpose bidirectional I/O port.
20.5.1 Port C Data Register (PTC) The port C data register contains a data latch for each of the six port C pins.
Bit 7 PTC $0002 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
0
0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
ALTERNATE FUNCTIONS
= Unimplemented
MCLK
Figure 20-7. Port C Data Register (PTC) PTC[5:0] -- Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. MCLK -- System Clock Bit The system clock is driven out of PTC2 when enabled by MCLKEN in PTC DDR7.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 323
I/O Ports
20.5.2 Data Direction Register C (DDRC) Data direction register C determines whether each port C pin is an input or an output. Writing a logic one to a DDRC bit enables the output buffer for the corresponding port C pin; a logic zero disables the output buffer.
Bit 7 DDRC $0006 Read: 6 5 4 3 2 1 Bit 0
0 MCLKEN DDRC5
0 0
DDRC4
0
DDRC3
0
DDRC2
0
DDRC1
0
DDRC0
0
Write: Reset: 0
= Unimplemented
Figure 20-8. Data Direction Register C (DDRC) MCLKEN -- MCLK Enable Bit This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, DDRC2 has no effect. Reset clears this bit. 1 = MCLK output enabled 0 = MCLK output disabled DDRC[5:0] -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1.
Advance Information 324 I/O Ports
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port C
Figure 20-9 shows the port C I/O logic. .
READ DDRC ($0006)
INTERNAL DATA BUS
WRITE DDRC ($0006) RESET WRITE PTC ($0002) PTCx PTCx DDRCx
READ PTC ($0002)
Figure 20-9. Port C I/O Circuit When bit DDRCx is a logic one, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic zero, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-4 summarizes the operation of the port C pins. Table 20-4. Port C Pin Functions
DDRC bit PTC Bit I/O Pin Mode Accesses to DDRC Read/Write 0 1 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTC Read Pin 0 Pin PTC[5:0] Write PTC2
2 2 X(1) X
Input, Hi-Z Output Input, Hi-Z(2) Output
DDRC[7] DDRC[7] DDRC[5:0] DDRC[5:0]
--
PTC[5:0](3) PTC[5:0]
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 325
I/O Ports 20.6 Port D
Port D is an 8 -bit special function port that shares seven of it's pins with the analog to digital converter and two with the TIMA and TIMB modules
20.6.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins.
Bit 7 PTD $0003 Read: 6 5 4 3 2 1 Bit 0
PTD7
Write: Reset:
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Unaffected by reset
Alternate Functions
R
ATD14/ TACLK
ATD13
ATD12/ TBCLK
ATD11
ATD10
ATD9
ATD8
Figure 20-10. Port D Data Register (PTD) PTD[7:0] -- Port D Data Bits PTD[7:0] are read/write, software programmable bits. Data direction of PTD[7:0] pins are under the control of the corresponding bit in data direction register D. ATD[14:8] -- ADC Channel Status Bits PTD6/ATD14/TACLK-PTD0/ATD8 are seven of the 15 analog-to-digital converter channels. The ATD channel select bits, CH[4:0], determine whether the PTD6/ATD14/TACLK-PTD0/ATD8 pins are ADC channels or general purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. Otherwise the data will reflect the value in the data latch.
NOTE:
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by the TIMA or TIMB. However, the DDRD bits always determine whether reading port D returns the states of the latches to logic 0.
Advance Information 326 I/O Ports
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port D
TACLK/TBCLK -- Timer clock input The PTD6/ATD14/TACLK pin is the external clock input for the TIMA. The PTD4/TBCLK pin is the external clock input for the TIMB.The prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK or PTD4/TBCLK as the TIM clock input (see TIMA Channel Status and Control Registers on page 424 and TIMB Status and Control Register on page 295). When not selected as the TIM clock, PTD6/TAClk and PTD4/TBCLK are available for general purpose I/O. While TACLK/TBCLK are selected, corresponding DDRD bits have no effect.
20.6.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output buffer.
Bit 7 DDRD $0007 Read: 6 5 4 3 2 1 Bit 0
DDRD7
Write: Reset: 0
DDRD6
0
DDRD5
0
DDRD4
0
DDRD3
0
DDRD2
0
DDRD1
0
DDRD0
0
Figure 20-11. Data Direction Register D (DDRD) DDRD[7:0] -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 20-12 shows the port D I/O logic. When bit DDRDx is a logic one, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic zero, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 327
I/O Ports
READ DDRD ($0007)
INTERNAL DATA BUS
WRITE DDRD ($0007) RESET WRITE PTD ($0003) PTDx PTDx DDRDx
READ PTD ($0003)
Figure 20-12. Port D I/O Circuit regardless of the state of its data direction bit. Table 20-5 summarizes the operation of the port D pins. Table 20-5. Port D Pin Functions
DDRD Bit PTD Bit I/O Pin Mode Accesses to DDRD Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTD Read Pin PTD[7:0] Write PTD[7:0](3) PTD[7:0]
X(1) X
Input, Hi-Z(2) Output
DDRD[7:0] DDRD[7:0]
Advance Information 328 I/O Ports
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port E
20.7 Port E
Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), two of its pins with the serial communications interface module (SCI) and four of its pins with the serial peripheral interface module (SPI).
20.7.1 Port E Data Register (PTE) The port E data register contains a data latch for each of the eight port E pins.
Bit 7 PTE $0008 Read: 6 5 4 3 2 1 Bit 0
PTE7
Write: Reset: Alternate SPSCK Function:
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
PTE0
Unaffected by reset
MOSI
MISO
SS
TACH1
TACH0
RxD
TxD
Figure 20-13. Port E Data Register (PTE) PTE[7:0] -- Port E Data Bits PTE[7:0] are read/write, software programmable bits. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. SPSCK -- SPI Serial Clock The PTE7/SPSCK pin is the serial clock input of a SPI slave module and serial clock output of a SPI master modules. When the SPE bit is clear, the PTE7/SPSCK pin is available for general-purpose I/O. MOSI -- Master Out/Slave In The PTE6/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear, the PTE6/MOSI pin is available for general-purpose I/O. See SPI Control Register (SPCR).
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 329
I/O Ports
MISO -- Master In/Slave Out The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O. See SPI Control Register (SPCR). SS -- Slave Select The PTE4/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and MODFEN bit is low, the PTE4/SS pin is available for general-purpose I/O. See SPI Control Register (SPCR). When the SPI is enabled as a slave, the DDRF0 bit in data direction register E (DDRE) has no effect on the PTE4/SS pin.
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SPI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 20-6. TACH[1:0] -- Timer A Channel I/O Bits The PTE3/TACH1-PTE2/TACH0 pins are the TIMA input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTE3/TACH1-PTE2/TACH0 pins are timer channel I/O pins or general-purpose I/O pins. See TIMA Channel Status and Control Registers on page 424.
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the TIMA. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 20-6.
Advance Information 330 I/O Ports
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port E
RxD -- SCI Receive Data Input The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See SCI Control Register 1. TxD -- SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See SCI Control Register 2.
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 20-6.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA I/O Ports
Advance Information 331
I/O Ports
20.7.2 Data Direction Register E (DDRE) Data direction register E determines whether each port E pin is an input or an output. Writing a logic one to a DDRE bit enables the output buffer for the corresponding port E pin; a logic zero disables the output buffer.
Bit 7 DDRE $000C Read: 6 5 4 3 2 1 Bit 0
DDRE7
Write: Reset: 0
DDRE6
0
DDRE5
0
DDRE4
0
DDRE3
0
DDRE2
0
DDRE1
0
DDRE0
0
Figure 20-14. Data Direction Register E (DDRE) DDRE[7:0] -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 20-15 shows the port E I/O logic.
READ DDRE ($000C)
INTERNAL DATA BUS
WRITE DDRE ($000C) RESET WRITE PTE ($0008) PTEx PTEx DDREx
READ PTE ($0008)
Figure 20-15. Port E I/O Circuit
Advance Information 332 I/O Ports
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I/O Ports Port E
When bit DDREx is a logic one, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic zero, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-6 summarizes the operation of the port E pins. Table 20-6. Port E Pin Functions
DDRE Bit PTE Bit I/O Pin Mode Accesses to DDRE Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTE Read Pin PTE[7:0] Write PTE[7:0](3) PTE[7:0]
X(1) X
Input, Hi-Z(2) Output
DDRE[7:0] DDRE[7:0]
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Advance Information 333
I/O Ports 20.8 Port F
Port F is a 7-bit special function port that shares four of its pins with the timer interface module (TIMA) and two of its pins with the timer interface module (TIMB)).
20.8.1 Port F Data Register (PTF) The port F data register contains a data latch for each of the seven port F pins.
Bit 7 PTF $0009 Read: Write: Reset: Alternate Function: Unaffected by reset 0 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 6 5 4 3 2 1 Bit 0
TBCH1
= Unimplemented
TBCH0
TACH5
TACH4
TACH3
TACH2
Figure 20-16. Port F Data Register (PTF) PTF[6:0] -- Port F Data Bits These read/write bits are software programmable. Data direction of each port F pin is under the control of the corresponding bit in data direction register F. Reset has no effect on PTF[6:0]. TACH[5:2] -- Timer A Channel I/O Bits The PTF3/TACH5-PTF0/TACH2 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTF3/TACH5-PTF0/TACH2 pins are timer channel I/O pins or general-purpose I/O pins.
Advance Information 334 I/O Ports
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I/O Ports Port F
TBCH[1:0] -- Timer B Channel I/O Bits The PTF5/TBCH1-PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1-PTF4/TBCH0 pins are timer channel I/O pins or general purpose I/O pins. See TIMB Status and Control Register on page 295.
NOTE:
Data direction register F(DDRF) does not affect the data direction of port F pins that are being used by TIMA and TIMB. However, the DDRF bits always determine whether reading port F returns the states of the latches or the states of the pins. See Table 20-7.
20.8.2 Data Direction Register F (DDRF) Data direction register F determines whether each port F pin is an input or an output. Writing a logic one to a DDRF bit enables the output buffer for the corresponding port F pin; a logic zero disables the output buffer.
Bit 7 DDRF $000D Read: Write: Reset: 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
= Unimplemented
Figure 20-17. Data Direction Register F (DDRF) DDRF[6:0] -- Data Direction Register F Bits These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins as inputs. 1 = Corresponding port F pin configured as output 0 = Corresponding port F pin configured as input
NOTE:
Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1.
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I/O Ports
Figure 20-18 shows the port F I/O logic.
READ DDRF ($000D)
INTERNAL DATA BUS
WRITE DDRF ($000D) RESET WRITE PTF ($0009) PTFx PTFx DDRFx
READ PTF ($0009)
Figure 20-18. Port F I/O Circuit When bit DDRFx is a logic one, reading address $0009 reads the PTFx data latch. When bit DDRFx is a logic zero, reading address $0009 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 20-7 summarizes the operation of the port F pins. Table 20-7. Port F Pin Functions
DDRF Bit PTF Bit I/O Pin Mode Accesses to DDRF Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTF Read Pin PTF[6:0] Write PTF[6:0](3) PTF[6:0]
X(1) X
Input, Hi-Z(2) Output
DDRF[6:0] DDRF[6:0]
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I/O Ports Port G
20.9 Port G
Port G is a 3-bit special function port that shares all of its pins with the Keyboard Interrupt Module (KBD).
20.9.1 Port G Data Register (PTG) The port G data register contains a data latch for each of the three port G pins.
Bit 7 Read: PTG $000A Write: Reset: Alternate Function = Unimplemented Unaffected by reset 6 5 4 3 2 1 Bit 0
0
0
0
0
0 PTG2 PTG1 PTG0
KBD2
KBD1
KBD0
Figure 20-19. Port G Data Register (PTG) PTG[2:0] -- Port G Data Bits These read/write bits are software-programmable. Data direction of each port G pin is under the control of the corresponding bit in data direction register G. Reset has no effect on PTG[2:0]. KBD[2:0] -- Keyboard Wakeup Pins The keyboard interrupt enable bits, KBIE[2:0], in the keyboard interrupt control register (KBICR), enable the port G pins as external interrupt pins. See Keyboard Module (KBD) on page 395. Enabling an external interrupt pin will override the corresponding DDRGx.
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I/O Ports
20.9.2 Data Direction Register G (DDRG) Data direction register G determines whether each port G pin is an input or an output. Writing a logic one to a DDRG bit enables the output buffer for the corresponding port G pin; a logic zero disables the output buffer.
Bit 7 DDRG $000E Read: Write: Reset: 0
6
5
4
3
2
1
Bit 0
0
0
0
0
0 DDRG2 DDRG1 DDRG0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-20. Data Direction Register G (DDRG) DDRG[2:0] -- Data Direction Register G Bits These read/write bits control port G data direction. Reset clears DDRG[2:0], configuring all port G pins as inputs. 1 = Corresponding port G pin configured as output 0 = Corresponding port G pin configured as input
NOTE:
Avoid glitches on port G pins by writing to the port G data register before changing data direction register G bits from 0 to 1. Figure 20-21 shows the port G I/O logic.
READ DDRG ($000E)
INTERNAL DATA BUS
WRITE DDRG ($000E) RESET WRITE PTG ($000A) PTGx PTGx DDRGx
READ PTG ($000A)
Figure 20-21. Port G I/O Circuit
Advance Information 338 I/O Ports MC68HC08AZ60A -- Rev 0.0 MOTOROLA
I/O Ports Port G
When bit DDRGx is a logic one, reading address $000A reads the PTGx data latch. When bit DDRGx is a logic zero, reading address $000A reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data. Table 20-8 summarises the operation of the port G pins. Table 20-8. Port G Pin Functions
DDRG Bit PTG Bit I/O Pin Mode Accesses to DDRG Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTG Read Pin PTG[2:0] Write PTG[2:0](3) PTG[2:0]
X(1) X
Input, Hi-Z(2) Output
DDRG[2:0] DDRG[2:0]
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I/O Ports 20.10 Port H
Port H is a 2-bit special function port that shares all of its pins with the Keyboard Interrupt Module (KBD).
20.10.1 Port H Data Register (PTH) The port H data register contains a data latch for each of the two port H pins.
Bit 7 Read: PTH $000B Write: Reset: Alternate Function = Unimplemented Unaffected by reset 6 5 4 3 2 1 Bit 0
0
0
0
0
0
0 PTH1 PTH0
KBD4
KBD3
Figure 20-22. Port H Data Register (PTH) PTH[1:0] -- Port H Data Bits These read/write bits are software-programmable. Data direction of each port H pin is under the control of the corresponding bit in data direction register H. Reset has no effect on port G data. KBD[4:3] -- Keyboard Wakeup Pins The keyboard interrupt enable bits, KBIE[4:3], in the keyboard interrupt control register (KBICR), enable the port H pins as external interrupt pins. See Keyboard Module (KBD).
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I/O Ports Port H
20.10.2 Data Direction Register H (DDRH) Data direction register H determines whether each port H pin is an input or an output. Writing a logic one to a DDRH bit enables the output buffer for the corresponding port H pin; a logic zero disables the output buffer.
Bit 7 DDRH $000F Read: Write: Reset: 0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0 DDRH1 DDRH0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-23. Data Direction Register H (DDRH) DDRH[1:0] -- Data direction register H bits These read/write bits control port H data direction. Reset clears DDRH[1:0], configuring all port H pins as inputs. 1 = Corresponding port H pin configured as output 0 = Corresponding port H pin configured as input
NOTE:
Avoid glitches on port H pins by writing to the port H data register before changing data direction register H bits from 0 to 1. Figure 20-24 shows the port H I/O logic.
READ DDRH ($000E)
INTERNAL DATA BUS
WRITE DDRH ($000E) RESET WRITE PTH ($000A) PTHx PTGx DDRHx
READ PTH ($000A)
Figure 20-24. Port H I/O Circuit
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I/O Ports
When bit DDRHx is a logic one, reading address $000B reads the PTHx data latch. When bit DDRHx is a logic zero, reading address $000B reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data. Table 20-9 summarises the operation of the port H pins. Table 20-9. Port H Pin Functions
DDRH Bit PTH Bit I/O Pin Mode Accesses to DDRH Read/Write 0 1
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
Accesses to PTH Read Pin PTH[1:0] Write PTH[1:0](3) PTH[1:0]
X(1) X
Input, Hi-Z(2) Output
DDRH[1:0] DDRH[1:0]
Advance Information 342 I/O Ports
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Advance Information -- MC68HC08AZ60A
Section 21. MSCAN08 Controller (MSCAN08)
21.1 Contents
21.2 21.3 21.4 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
21.5 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 21.5.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 21.5.2 Receive Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 21.5.3 Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 21.6 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . 352
21.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 21.7.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . .358 21.7.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.8 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . 359
21.9 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 21.9.1 MSCAN08 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.9.2 MSCAN08 Soft Reset Mode . . . . . . . . . . . . . . . . . . . . . . . 362 21.9.3 MSCAN08 Power Down Mode . . . . . . . . . . . . . . . . . . . . . 363 21.9.4 CPU Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 21.9.5 Programmable Wakeup Function . . . . . . . . . . . . . . . . . . 364 21.10 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 21.11 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 21.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 21.13 Programmer's Model of Message Storage . . . . . . . . . . . . . 368 21.13.1 Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . 369 21.13.2 Identifier Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
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MSCAN08 Controller (MSCAN08)
21.13.3 Data Length Register (DLR) . . . . . . . . . . . . . . . . . . . . . . 373 21.13.4 Data Segment Registers (DSRn). . . . . . . . . . . . . . . . . . . 373 21.13.5 Transmit Buffer Priority Registers . . . . . . . . . . . . . . . . . 374 21.14 Programmer's Model of Control Registers . . . . . . . . . . . .374 21.14.1 MSCAN08 Module Control Register 0 . . . . . . . . . . . . . . 377 21.14.2 MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . 379 21.14.3 MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . 380 21.14.4 MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . 381 21.14.5 MSCAN08 Receiver Flag Register (CRFLG). . . . . . . . . . 383 21.14.6 MSCAN08 Receiver Interrupt Enable Register . . . . . . . 385 21.14.7 MSCAN08 Transmitter Flag Register . . . . . . . . . . . . . . . 387 21.14.8 MSCAN08 Transmitter Control Register . . . . . . . . . . . .388 21.14.9 MSCAN08 Identifier Acceptance Control Register . . . . 389 21.14.10 MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . 391 21.14.11 MSCAN08 Transmit Error Counter . . . . . . . . . . . . . . . . . 391 21.14.12 MSCAN08 Identifier Acceptance Registers . . . . . . . . . . 392 21.14.13 MSCAN08 Identifier Mask Registers (CIDMR0-3) . . . . .393
21.2 Introduction
The MSCAN08 is the specific implementation of the Motorola scalable controller area network (MSCAN) concept targeted for the Motorola M68HC08 Microcontroller Family. The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification dated September 1991. The CAN protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness and required bandwidth. MSCAN08 utilizes an advanced buffer arrangement, resulting in a predictable real-time behavior, and simplifies the application software.
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MSCAN08 Controller (MSCAN08) Features
21.3 Features
Basic features of the MSCAN08 are: * * Modular Architecture Implementation of the CAN Protocol -- Version 2.0A/B - Standard and Extended Data Frames. - 0-8 Bytes Data Length. - Programmable Bit Rate up to 1 Mbps Depending on the Actual Bit Timing and the Clock Jitter of the PLL * * * * Support for Remote Frames Double-Buffered Receive Storage Scheme Triple-Buffered Transmit Storage Scheme with Internal Prioritisation Using a "Local Priority" Concept Flexible Maskable Identifier Filter Supports Alternatively One Full Size Extended Identifier Filter or Two 16-Bit Filters or Four 8-Bit Filters Programmable Wakeup Functionality with Integrated Low-Pass Filter Programmable Loop-Back Mode Supports Self-Test Operation Separate Signalling and Interrupt Capabilities for All CAN Receiver and Transmitter Error States (Warning, Error Passive, Bus Off) Programmable MSCAN08 Clock Source Either CPU Bus Clock or Crystal Oscillator Output Programmable Link to On-Chip Timer Interface Module (TIMB) for Time-Stamping and Network Synchronization Low-Power Sleep Mode
* * *
* * *
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MSCAN08 Controller (MSCAN08) 21.4 External Pins
The MSCAN08 uses two external pins, one input (RxCAN) and one output (TxCAN). The TxCAN output pin represents the logic level on the CAN: 0 is for a dominant state, and 1 is for a recessive state. A typical CAN system with MSCAN08 is shown in Figure 21-1.
CAN STATION 1 CAN NODE 1 CAN NODE 2 CAN NODE N
MCU
CAN CONTROLLER (MSCAN08)
TXCAN
RXCAN
TRANSCEIVER
CAN_H
CAN_L C A N BUS
Figure 21-1. The CAN System Each CAN station is connected physically to the CAN bus lines through a transceiver chip. The transceiver is capable of driving the large current needed for the CAN and has current protection against defective CAN or defective stations.
Advance Information 346 MSCAN08 Controller (MSCAN08)
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MSCAN08 Controller (MSCAN08) Message Storage
21.5 Message Storage
MSCAN08 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
21.5.1 Background Modern application layer software is built under two fundamental assumptions: 1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus between two messages. Such nodes will arbitrate for the bus right after sending the previous message and will only release the bus in case of lost arbitration. 2. The internal message queue within any CAN node is organized as such that the highest priority message will be sent out first if more than one message is ready to be sent. Above behaviour cannot be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no buffer would then be ready for transmission and the bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN08 has three transmit buffers.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 347
MSCAN08 Controller (MSCAN08)
The second requirement calls for some sort of internal prioritisation which the MSCAN08 implements with the "local priority" concept described in Receive Structures on page 348.
21.5.2 Receive Structures The received messages are stored in a 2-stage input first in first out (FIFO). The two message buffers are mapped using a Ping Pong arrangement into a single memory area (see Figure 21-2). While the background receive buffer (RxBG) is exclusively associated to the MSCAN08, the foreground receive buffer (RxFG) is addressable by the CPU08. This scheme simplifies the handler software, because only one address area is applicable for the receive process. Both buffers have a size of 13 bytes to store the CAN control bits, the identifier (standard or extended), and the data content (for details, see Programmer's Model of Message Storage on page 368). The receiver full flag (RXF) in the MSCAN08 receiver flag register (CRFLG) (see MSCAN08 Receiver Flag Register (CRFLG) on page 383), signals the status of the foreground receive buffer. When the buffer contains a correctly received message with matching identifier, this flag is set. On reception, each message is checked to see if it passes the filter (for details see Identifier Acceptance Filter on page 352) and in parallel is written into RxBG. The MSCAN08 copies the content of RxBG into RxFG(1), sets the RXF flag, and generates a receive interrupt to the CPU(2). The user's receive handler has to read the received message from RxFG and to reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message which can follow immediately after the IFS field of the CAN frame, is received into RxBG. The overwriting of the background buffer is independent of the identifier filter function.
1. Only if the RXF flag is not set. 2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also.
Advance Information 348 MSCAN08 Controller (MSCAN08)
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MSCAN08 Controller (MSCAN08) Message Storage
When the MSCAN08 module is transmitting, the MSCAN08 receives its own messages into the background receive buffer, RxBG. It does NOT overwrite RxFG, generate a receive interrupt or acknowledge its own messages on the CAN bus. The exception to this rule is in loop-back mode (see MSCAN08 Module Control Register 1 on page 379), where the MSCAN08 treats its own messages exactly like all other incoming messages. The MSCAN08 receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN08 must be prepared to become receiver. An overrun condition occurs when both the foreground and the background receive message buffers are filled with correctly received messages with accepted identifiers and another message is correctly received from the bus with an accepted identifier. The latter message will be discarded and an error interrupt with overrun indication will be generated if enabled. The MSCAN08 is still able to transmit messages with both receive message buffers filled, but all incoming messages are discarded.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 349
MSCAN08 Controller (MSCAN08)
MSCAN08
RxBG
CPU08 Ibus
RxFG
RXF
Tx0
TXE
PRIO
Tx1
TXE
PRIO
Tx2
TXE
PRIO
Figure 21-2. User Model for Message Buffer Organization
Advance Information 350 MSCAN08 Controller (MSCAN08)
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MSCAN08 Controller (MSCAN08) Message Storage
21.5.3 Transmit Structures The MSCAN08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers are arranged as shown in Figure 21-2. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Programmer's Model of Message Storage on page 368). An additional transmit buffer priority register (TBPR) contains an 8-bit "local priority" field (PRIO) (see Transmit Buffer Priority Registers on page 374). To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see MSCAN08 Transmitter Flag Register on page 387). The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers. Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag. The MSCAN08 then will schedule the message for transmission and will signal the successful transmission of the buffer by setting the TXE flag. A transmit interrupt is generated(1) when TXE is set and can be used to drive the application software to re-load the buffer. In case more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN08 uses the local priority setting of the three buffers for prioritisation. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software sets this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being emitted from this node. The lowest binary value of the PRIO field is defined as the highest priority.
1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE also.
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MSCAN08 Controller (MSCAN08)
The internal scheduling process takes place whenever the MSCAN08 arbitrates for the bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message being set up in one of the three transmit buffers. As messages that are already under transmission cannot be aborted, the user has to request the abort by setting the corresponding abort request flag (ABTRQ) in the transmission control register (CTCR). The MSCAN08 will then grant the request, if possible, by setting the corresponding abort request acknowledge (ABTAK) and the TXE flag in order to release the buffer and by generating a transmit interrupt. The transmit interrupt handler software can tell from the setting of the ABTAK flag whether the message was actually aborted (ABTAK = 1) or sent (ABTAK = 0).
21.6 Identifier Acceptance Filter
The Identifier Acceptance Registers (CIDAR0-3) define the acceptance patterns of the standard or extended identifier (ID10-ID0 or ID28-ID0). Any of these bits can be marked `don't care' in the Identifier Mask Registers (CIDMR0-3). A filter hit is indicated to the application on software by a set RXF (Receive Buffer Full Flag, see MSCAN08 Receiver Flag Register (CRFLG) on page 383) and two bits in the Identifier Acceptance Control Register (see MSCAN08 Identifier Acceptance Control Register on page 389). These Identifier Hit Flags (IDHIT1-0) clearly identify the filter section that caused the acceptance. They simplify the application software's task to identify the cause of the receiver interrupt. In case that more than one hit occurs (two or more filters match) the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes:
Advance Information 352 MSCAN08 Controller (MSCAN08)
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MSCAN08 Controller (MSCAN08) Identifier Acceptance Filter
*
Single identifier acceptance filter, each to be applied to a) the full 29 bits of the extended identifier and to the following bits of the CAN frame: RTR, IDE, SRR or b) the 11 bits of the standard identifier plus the RTR and IDE bits of CAN 2.0A/B messages. This mode implements a single filter for a full length CAN 2.0B compliant extended identifier. Figure 21-3 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3) produces a filter 0 hit. Two identifier acceptance filters, each to be applied to a) the 14 most significant bits of the extended identifier plus the SRR and the IDE bits of CAN2.0B messages, or b) the 11 bits of the identifier plus the RTR and IDE bits of CAN 2.0A/B messages. Figure 21-4 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3) produces filter 0 and 1 hits. Four identifier acceptance filters, each to be applied to the first eight bits of the identifier. This mode implements four independent filters for the first eight bits of a CAN 2.0A/B compliant standard identifier. Figure 21-5 shows how the 32-bit filter bank (CIDAR03, CIDMR0-3) produces filter 0 to 3 hits. Closed filter. No CAN message will be copied into the foreground buffer RxFG, and the RXF flag will never be set.
*
*
*
ID28 ID10
IDR0 IDR0
ID21 ID20 ID3 ID2
IDR1 IDR1
ID15 ID14 IDE ID10
IDR2 IDR2
ID7 ID6 ID3 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0 AM7
CIDMR1
AM0 AM7
CIDMR2
AM0 AM7
CIDMR3
AM0
AC7
CIDAR0
AC0 AC7
CIDAR1
AC0 AC7
CIDAR2
AC0 AC7
CIDAR3
AC0
ID Accepted (Filter 0 Hit)
Figure 21-3. Single 32-Bit Maskable Identifier Acceptance Filter
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MSCAN08 Controller (MSCAN08)
ID28 ID10
IDR0 IDR0
ID21 ID20 ID3 ID2
IDR1 IDR1
ID15 ID14 IDE ID10
IDR2 IDR2
ID7 ID6 ID3 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0 AM7
CIDMR1
AM0
AC7
CIDAR0
AC0 AC7
CIDAR1
AC0
ID ACCEPTED (FILTER 0 HIT)
AM7
CIDMR2
AM0 AM7
CIDMR3
AM0
AC7
CIDAR2
AC0 AC7
CIDAR3
AC0
ID ACCEPTED (FILTER 1 HIT)
Figure 21-4. Dual 16-Bit Maskable Acceptance Filters
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MSCAN08 Controller (MSCAN08) Identifier Acceptance Filter
.
ID28 ID10
IDR0 IDR0
ID21 ID20 ID3 ID2
IDR1 IDR1
ID15 ID14 IDE ID10
IDR2 IDR2
ID7 ID6 ID3 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0
AC7
CIDAR0
AC0
ID ACCEPTED (FILTER 0 HIT)
AM7
CIDMR1
AM0
AC7
CIDAR1
AC0
ID ACCEPTED (FILTER 1 HIT)
AM7
CIDMR2
AM0
AC7
CIDAR2
AC0
ID ACCEPTED (FILTER 2 HIT)
AM7
CIDMR3
AM0
AC7
CIDAR3
AC0
ID ACCEPTED (FILTER 3 HIT)
Figure 21-5. Quadruple 8-Bit Maskable Acceptance Filters
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MSCAN08 Controller (MSCAN08)
21.6.1 MSCAN Extended ID Rejected if Stuff Bit Between ID16 and ID15 For 32-bit and 16-bit identifier acceptance modes, an extended ID CAN frame with a stuff bit between ID16 and ID15 can be erroneously rejected, depending on IDAR0, IDAR1, and IDMR1. Extended IDs (ID28-ID0) which generate a stuff bit between ID16 and ID15: IDAR0 ******** IDAR1 ***1111x IDAR2 xxxxxxxx IDAR3 xxxxxxxx
where x = 0 or 1 (don't care) * = pattern for ID28 to ID18 (see following). Affected extended IDs (ID28 - ID18) patterns: a) xxxxxxxxx01 exceptions: 00000000001 01111100001 xxxx1000001 except 11111000001 b) c) d) e) f) g) xxxxx100000 xxxx0111111 x0111110000 10000000000 11111111111 10000011111 exception: exception: 01111100000 00000111111
When an affected ID is received, an incorrect value is compared to the 2nd byte of the filter (IDAR1 and IDAR5, plus IDAR3 and IDAR7 in 16bit mode). This incorrect value is the shift register contents before ID15 is shifted in (i.e. right shifted by 1). 21.6.1.1 Work- around If the problematic IDs cannot be avoided, the workaround is to mask certain bits with IDMR1 (and IDMR5, plus IDMR3 and IDMR7 in 16-bit mode).
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MSCAN08 Controller (MSCAN08) Interrupts
Example 1: to receive the message IDs xxxx xxxx x011 111x xxxx xxxx xxxx xxxx IDMR1 etc. must be 111x xxx1, i.e. ID20,19,18,15 must be masked. Example 2: to receive the message IDs xxxx 0111 1111 111x xxxx xxxx xxxx xxxx IDMR1 etc. must be 1xxx xxx1, i.e. ID20 and ID15 must be masked. In general, using IDMR1 etc. 1111 xxx1, i.e. masking ID20,19,18,SRR,15, hides the problem.
21.7 Interrupts
The MSCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked (for details see MSCAN08 Receiver Flag Register (CRFLG) on page 383, to MSCAN08 Transmitter Control Register on page 388). * Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXE flags of the empty message buffers are set. Receive Interrupt: A message has been received successfully and loaded into the foreground receive buffer. This interrupt will be emitted immediately after receiving the EOF symbol. The RXF flag is set. Wakeup Interrupt: An activity on the CAN bus occurred during MSCAN08 internal sleep mode or power-down mode (provided SLPAK = WUPIE = 1). Error Interrupt: An overrun, error, or warning condition occurred. The receiver flag register (CRFLG) will indicate one of the following conditions: - Overrun: An overrun condition as described in Receive Structures on page 348, has occurred. - Receiver Warning: The receive error counter has reached the CPU Warning limit of 96.
*
*
*
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MSCAN08 Controller (MSCAN08)
- Transmitter Warning: The transmit error counter has reached the CPU Warning limit of 96. - Receiver Error Passive: The receive error counter has exceeded the error passive limit of 127 and MSCAN08 has gone to error passive state. - Transmitter Error Passive: The transmit error counter has exceeded the error passive limit of 127 and MSCAN08 has gone to error passive state. - Bus Off: The transmit error counter has exceeded 255 and MSCAN08 has gone to bus off state.
21.7.1 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the MSCAN08 receiver flag register (CRFLG) or the MSCAN08 transmitter flag register (CTFLG). Interrupts are pending as long as one of the corresponding flags is set. The flags in the above registers must be reset within the interrupt handler in order to handshake the interrupt. The flags are reset through writing a `1' to the corresponding bit position. A flag cannot be cleared if the respective condition still prevails.
NOTE:
Bit manipulation instructions (BSET) shall not be used to clear interrupt flags.
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MSCAN08 Controller (MSCAN08) Protocol Violation Protection
21.7.2 Interrupt Vectors The MSCAN08 supports four interrupt vectors as shown in Table 21-1. The vector addresses and the relative interrupt priority are defined in Table 2-1. Table 21-1. MSCAN08 Interrupt Vector Addresses
Function
Wakeup
Source
WUPIF
Local Mask
WUPIE
Global Mask
RWRNIF TWRNIF Error Interrupts RERRIF TERRIF BOFFIF OVRIF Receive Transmit RXF TXE0 TXE1 TXE2
RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE TXEIE0 TXEIE1 TXEIE2 I Bit
21.8 Protocol Violation Protection
The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: * * The receive and transmit error counters cannot be written or otherwise manipulated. All registers which control the configuration of the MSCAN08 can not be modified while the MSCAN08 is on-line. The SFTRES bit in the MSCAN08 module control register (see MSCAN08 Module Control Register 0 on page 377) serves as a lock to protect the following registers: - MSCAN08 module control register 1 (CMCR1) - MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1) - MSCAN08 identifier acceptance control register (CIDAC) - MSCAN08 identifier acceptance registers (CIDAR0-3)
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MSCAN08 Controller (MSCAN08)
- MSCAN08 identifier mask registers (CIDMR0-3) * The TxCAN pin is forced to recessive when the MSCAN08 is in any of the Low Power Modes.
21.9 Low Power Modes
In addition to normal mode, the MSCAN08 has three modes with reduced power consumption: Sleep, Soft Reset and Power Down modes. In Sleep and Soft Reset mode, power consumption is reduced by stopping all clocks except those to access the registers. In Power Down mode, all clocks are stopped and no power is consumed. The WAIT and STOP instructions put the MCU in low power consumption stand-by modes. summarizes the combinations of MSCAN08 and CPU modes. A particular combination of modes is entered for the given settings of the bits SLPAK and SFTRES. For all modes, an MSCAN wake-up interrupt can occur only if SLPAK=WUPIE=1. . Table 21-2 MSCAN08 vs CPU Operating Modes
CPU Mode MSCAN Mode STOP
Power Down Sleep Soft Reset Normal 1. `X' means don't care. SLPAK = X(1) SFTRES = X SLPAK = 1 SFTRES = 0 SLPAK = 0 SFTRES = 1 SLPAK = 0 SFTRES = 0
WAIT or RUN
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MSCAN08 Controller (MSCAN08) Low Power Modes
21.9.1 MSCAN08 Sleep Mode The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit in the module configuration register (see Figure 21-6). The time when the MSCAN08 enters Sleep mode depends on its activity: * * * if it is transmitting, it continues to transmit until there is no more message to be transmitted, and then goes into Sleep mode if it is receiving, it waits for the end of this message and then goes into Sleep mode if it is neither transmitting or receiving, it will immediately go into Sleep mode
NOTE:
The application software must avoid setting up a transmission (by clearing or more TXE flags) and immediately request Sleep mode (by setting SLPRQ). It then depends on the exact sequence of operations whether MSCAN08 starts transmitting or goes into Sleep mode directly. During Sleep mode, the SLPAK flag is set. The application software should use SLPAK as a handshake indication for the request (SLPRQ) to go into Sleep mode. When in Sleep mode, the MSCAN08 stops its internal clocks. However, clocks to allow register accesses still run. If the MSCAN08 is in buss-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. The TxCAN pin stays in recessive state. If RXF=1, the message can be read and RXF can be cleared. Copying of RxGB into RxFG doesn't take place while in Sleep mode. It is possible to access the transmit buffers and to clear the TXE flags. No message abort takes place while in Sleep mode. The MSCAN08 leaves Sleep mode (wake-up) when: * * * bus activity occurs or the MCU clears the SLPRQ bit or the MCU sets the SFTRES bit
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MSCAN08 Controller (MSCAN08)
MSCAN08 Running SLPRQ = 0 SLPAK = 0 MCU or MSCAN08 MCU
MSCAN08 Sleeping SLPRQ = 1 SLPAK = 1
Sleep Request SLPRQ = 1 SLPAK = 0
MSCAN08
Figure 21-6. Sleep Request/Acknowledge Cycle
NOTE:
The MCU cannot clear the SLPRQ bit before the MSCAN08 is in Sleep mode (SLPAK=1). After wake-up, the MSCAN08 waits for 11 consecutive recessive bits to synchronize to the bus. As a consequence, if the MSCAN08 is wokenup by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before Sleep mode was entered. All pending actions are executed upon wake-up: copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN08 is still in bus-off state after Sleep mode was left, it continues counting the 128*11 consecutive recessive bits.
21.9.2 MSCAN08 Soft Reset Mode In Soft Reset mode, the MSCAN08 is stopped. Registers can still be accessed. This mode is used to initialize the module configuration, bit timing and the CAN message filter. See MSCAN08 Module Control Register 0 on page 377 for a complete description of the Soft Reset mode.
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MSCAN08 Controller (MSCAN08) Low Power Modes
When setting the SFTRES bit, the MSCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations.
NOTE:
The user is responsible to take care that the MSCAN08 is not active when Soft Reset mode is entered. The recommended procedure is to bring the MSCAN08 into Sleep mode before the SFTRES bit is set.
21.9.3 MSCAN08 Power Down Mode The MSCAN08 is in Power Down mode when the CPU is in Stop mode. When entering the Power Down mode, the MSCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations.
NOTE:
The user is responsible to take care that the MSCAN08 is not active when Power Down mode is entered. The recommended procedure is to bring the MSCAN08 into Sleep mode before the STOP instruction is executed. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN08 drives the TxCAN pin into recessive state. In Power Down mode, no registers can be accessed. MSCAN08 bus activity can wake the MCU from CPU Stop/MSCAN08 power-down mode. However, until the oscillator starts up and synchronisation is achieved the MSCAN08 will not respond to incoming data.
21.9.4 CPU Wait Mode The MSCAN08 module remains active during CPU wait mode. The MSCAN08 will stay synchronized to the CAN bus and generates transmit, receive, and error interrupts to the CPU, if enabled. Any such interrupt will bring the MCU out of wait mode.
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MSCAN08 Controller (MSCAN08)
21.9.5 Programmable Wakeup Function The MSCAN08 can be programmed to apply a low-pass filter function to the RxCAN input line while in internal sleep mode (see information on control bit WUPM in MSCAN08 Module Control Register 1 on page 379). This feature can be used to protect the MSCAN08 from wake-up due to short glitches on the CAN bus lines. Such glitches can result from electromagnetic inference within noisy environments.
21.10 Timer Link
The MSCAN08 will generate a timer signal whenever a valid frame has been received. Because the CAN specification defines a frame to be valid if no errors occurred before the EOF field has been transmitted successfully, the timer signal will be generated right after the EOF. A pulse of one bit time is generated. As the MSCAN08 receiver engine also receives the frames being sent by itself, a timer signal also will be generated after a successful transmission. The previously described timer signal can be routed into the on-chip Timer Interface Module B (TIMB).This signal is connected to the Channel 0 input under the control of the timer link enable (TLNKEN) bit in the CMCR0. After the TIMB module has been programmed to capture rising edge events, it can be used under software control to generate 16-bit time stamps which can be stored with the received message.
21.11 Clock System
Figure 21-7 shows the structure of the MSCAN08 clock generation circuitry and its interaction with the clock generation module (CGM). With this flexible clocking scheme the MSCAN08 is able to handle CAN bus rates ranging from 10 kbps up to 1 Mbps.
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MSCAN08 Controller (MSCAN08) Clock System
CGMXCLK OSC
/2
CGMOUT (TO SIM) BCS PLL
/2
CGM MSCAN08 (2 * BUS FREQ.)
/2
MSCANCLK PRESCALER CLKSRC (1 .. 64)
Figure 21-7. Clocking Scheme The clock source bit (CLKSRC) in the MSCAN08 module control register (CMCR1) (see MSCAN08 Module Control Register 0 on page 377) defines whether the MSCAN08 is connected to the output of the crystal oscillator or to the PLL output. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met.
NOTE:
If the system clock is generated from a PLL, it is recommended to select the crystal clock source rather than the system clock source due to jitter considerations, especially at faster CAN bus rates. A programmable prescaler is used to generate out of the MSCAN08 clock the time quanta (Tq) clock. A time quantum is the atomic unit of time handled by the MSCAN08.
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MSCAN08 Controller (MSCAN08)
fTq =
fMSCANCLK Presc value
A bit time is subdivided into three segments(1)(see Figure 21-8). * * SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. Time segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. Time segment 2: This segment represents PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
*
Bit rate=
fTq No. of time quanta
The synchronization jump width (SJW) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The above parameters can be set by programming the bus timing registers, CBTR0-CBTR1, see MSCAN08 Bus Timing Register 0 on page 380 and MSCAN08 Bus Timing Register 1 on page 381).
NOTE:
It is the user's responsibility to make sure that the bit timing settings are in compliance with the CAN standard, Table 21-8 gives an overview on the CAN conforming segment settings and the related parameter values.
1. For further explanation of the underlying concepts please refer to ISO/DIS 11 519-1, Section 10.3.
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MSCAN08 Controller (MSCAN08) Clock System
NRZ SIGNAL
SYNC _SEG 1
TIME SEGMENT 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8... 25 TIME QUANTA = 1 BIT TIME
TIME SEG. 2 (PHASE_SEG2) 2 ... 8
SAMPLE POINT (SINGLE OR TRIPLE SAMPLING)
Figure 21-8. Segments Within the Bit Time Table 21-3. Time segment syntax
SYNC_SEG Transmit point System expects transitions to occur on the bus during this period. A node in transmit mode will transfer a new value to the CAN bus at this point. A node in receive mode will sample the bus at this point. If the three samples per bit option is selected then this point marks the position of the third sample.
Sample point
Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16
TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15
Time Segment 2 2 3 4 5 6 7 8
TSEG2 1 2 3 4 5 6 7
Synchron. Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4
SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3
Table 21-4. CAN Standard Compliant Bit Time Segment Settings
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MSCAN08 Controller (MSCAN08) 21.12 Memory Map
The MSCAN08 occupies 128 bytes in the CPU08 memory space, as shown in Figure 21-9.
$0500 $0508 $0509 $050D $050E $050F $0510 $0517 $0518 $053F $0540 $054F $0550 $055F $0560 $056F $0570 $057F CONTROL REGISTERS 9 BYTES RESERVED 5 BYTES ERROR COUNTERS 2 BYTES IDENTIFIER FILTER 8 BYTES RESERVED 40 BYTES RECEIVE BUFFER TRANSMIT BUFFER 0 TRANSMIT BUFFER 1 TRANSMIT BUFFER 2
Figure 21-9. MSCAN08 Memory Map
21.13 Programmer's Model of Message Storage
This section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers.
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MSCAN08 Controller (MSCAN08) Programmer's Model of Message Storage
Addr(1) $05b0 $05b1 $05b2 $05b3 $05b4 $05b5 $05b6 $05b7 $05b8 $05b9 $05bA $05bB $05bC $05bD $05bE $05bF
Register Name IDENTIFIER REGISTER 0 IDENTIFIER REGISTER 1 IDENTIFIER REGISTER 2 IDENTIFIER REGISTER 3 DATA SEGMENT REGISTER 0 DATA SEGMENT REGISTER 1 DATA SEGMENT REGISTER 2 DATA SEGMENT REGISTER 3 DATA SEGMENT REGISTER 4 DATA SEGMENT REGISTER 5 DATA SEGMENT REGISTER 6 DATA SEGMENT REGISTER 7 DATA LENGTH REGISTER TRANSMIT BUFFER PRIORITY REGISTER(2) UNUSED UNUSED
1. Where b equals the following: b=4 for Receive Buffer b=5 for Transmit Buffer 0 b=6 for Transmit Buffer 1 b=7 for Transmit Buffer 2 2. Not applicable for receive buffers
Figure 21-10. Message Buffer Organization
21.13.1 Message Buffer Outline Figure 21-11 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 21-12. All bits of the 13-byte data structure are undefined out of reset.
NOTE:
The foreground receive buffer can be read anytime but cannot be written. The transmit buffers can be read or written anytime.
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MSCAN08 Controller (MSCAN08)
21.13.2 Identifier Registers The identifiers consist of either 11 bits (ID10-ID0) for the standard, or 29 bits (ID28-ID0) for the extended format. ID10/28 is the most significant bit and is transmitted first on the bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. SRR -- Substitute Remote Request This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and will be stored as received on the CAN bus for receive buffers.
Addr $05b0 $05b1 $05b2 $05b3 $05b4 $05b5 Register
Read: IDR0 Write: Read: IDR1 Write: Read: IDR2 Write: Read: IDR3 Write: Read: DSR0 Write: Read: DSR1 Write: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
Bit 7
6
5
4
3
2
1
Bit 0
Figure 21-11. Receive/Transmit Message Buffer Extended Identifier (IDRn) (Sheet 1 of 2)
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MSCAN08 Controller (MSCAN08) Programmer's Model of Message Storage
Addr $05b6 $05b7 $05b8 $05b9 $05bA $05bB $05bC
Register
Read: DSR2 Write: Read: DSR3 Write: Read: DSR4 Write: Read: DSR5 Write: Read: DSR6 Write: Read: DSR7 Write: Read: DLR Write:
Bit 7
DB7
6
DB6
5
DB5
4
DB4
3
DB3
2
DB2
1
DB1
Bit 0
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
= Unimplemented
Figure 21-11. Receive/Transmit Message Buffer Extended Identifier (IDRn) (Sheet 2 of 2)
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MSCAN08 Controller (MSCAN08)
Addr $05b0
Register
Read: IDR0 Write: Read:
Bit 7
ID10
6
ID9
5
ID8
4
ID7
3
ID6
2
ID5
1
ID4
Bit 0
ID3
$05b1
IDR1 Write: Read:
ID2
ID1
ID0
RTR
IDE(=0)
$05b2
IDR2 Write: Read:
$05b3
IDR3 Write:
= Unimplemented
Figure 21-12. Standard Identifier Mapping IDE -- ID Extended This flag indicates whether the extended or standard identifier format is applied in this buffer. In case of a receive buffer, the flag is set as being received and indicates to the CPU how to process the buffer identifier registers. In case of a transmit buffer, the flag indicates to the MSCAN08 what type of identifier to send. 1 = Extended format, 29 bits 0 = Standard format, 11 bits RTR -- Remote Transmission Request This flag reflects the status of the remote transmission request bit in the CAN frame. In case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 1 = Remote frame 0 = Data frame
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MSCAN08 Controller (MSCAN08) Programmer's Model of Message Storage
21.13.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. DLC3-DLC0 -- Data Length Code Bits The data length code contains the number of bytes (data byte count) of the respective message. At transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 21-5 shows the effect of setting the DLC bits. Table 21-5. Data Length Codes
Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8
21.13.4 Data Segment Registers (DSRn) The eight data segment registers contain the data to be transmitted or received. The number of bytes to be transmitted or being received is determined by the data length code in the corresponding DLR.
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MSCAN08 Controller (MSCAN08)
21.13.5 Transmit Buffer Priority Registers
Address:
$05bD Bit 7 6 PRIO6 u 5 PRIO5 u 4 PRIO4 u 3 PRIO3 u 2 PRIO2 u 1 PRIO1 u Bit 0 PRIO0 u
Read: PRIO7 Write: Reset: u
Figure 21-13. Transmit Buffer Priority Register (TBPR) PRIO7-PRIO0 -- Local Priority This field defines the local priority of the associated message buffer. The local priority is used for the internal prioritisation process of the MSCAN08 and is defined to be highest for the smallest binary number. The MSCAN08 implements the following internal prioritisation mechanism: * * * All transmission buffers with a cleared TXE flag participate in the prioritisation right before the SOF is sent. The transmission buffer with the lowest local priority field wins the prioritisation. In case more than one buffer has the same lowest priority, the message buffer with the lower index number wins.
21.14 Programmer's Model of Control Registers
The programmer's model has been laid out for maximum simplicity and efficiency. Figure 21-14 gives an overview on the control register block of the MSCAN08.
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
Addr $0500
Register Read: CMCR0 Write: Read:
Bit 7 0
6 0
5 0
4 SYNCH
3 TLNKEN
2 SLPAK
1 SLPRQ
Bit 0 SFTRES
0
0
0
0
0 LOOPB WUPM CLKSRC
$0501
CMCR1 Write: Read:
$0502
CBTR0 Write: Read:
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
$0503
CBTR1 Write: Read:
SAMP
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
$0504
CRFLG Write: Read:
WUPIF
RWRNIF
TWRNIF
RERRIF
TERRIF
BOFFIF
OVRIF
RXF
$0505
CRIER Write: Read:
WUPIE 0
RWRNIE ABTAK2
TWRNIE ABTAK1
RERRIE ABTAK0
TERRIE 0
BOFFIE
OVRIE
RXFIE
$0506
CTFLG Write: Read: 0 ABTRQ2 Write: Read: 0 0 IDAM1 Write: Read: IDAM0 0 ABTRQ1 ABTRQ0 0
TXE2
TXE1
TXE0
$0507
CTCR
TXEIE2 0
TXEIE1 IDHIT1
TXEIE0 IDHIT0
$0508
CIDAC
$0509
Reserved Write:
R
R
R
R
R
R
R
R
= Unimplemented
R
= Reserved
Figure 21-14. MSCAN08 Control Register Structure
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MSCAN08 Controller (MSCAN08)
Addr $050E
Register Read: CRXERR Write: Read:
Bit 7 RXERR7
6 RXERR6
5 RXERR5
4 RXERR4
3 RXERR3
2 RXERR2
1 RXERR1
Bit 0 RXERR0
$050F
CTXERR Write: Read:
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
$0510
CIDAR0 Write: Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0511
CIDAR1 Write: Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0512
CIDAR2 Write: Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0513
CIDAR3 Write: Read:
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0514
CIDMR0 Write: Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
$0515
CIDMR1 Write: Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
$0516
CIDMR2 Write: Read:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
$0517
CIDMR3 Write:
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Figure 21-14. MSCAN08 Control Register Structure (Continued)
Advance Information 376 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
21.14.1 MSCAN08 Module Control Register 0
Address:
$0500 Bit 7 6 0 5 0 4 SYNCH TLNKEN 3 2 SLPAK SLPRQ 0 0 SFTRES 1 1 Bit 0
Read: Write: Reset:
0
0
0
0
0
0
= Unimplemented
Figure 21-15. Module Control Register 0 (CMCR0) SYNCH -- Synchronized Status This bit indicates whether the MSCAN08 is synchronized to the CAN bus and as such can participate in the communication process. 1 = MSCAN08 synchronized to the CAN bus 0 = MSCAN08 not synchronized to the CAN bus TLNKEN -- Timer Enable This flag is used to establish a link between the MSCAN08 and the on-chip timer (see Timer Link on page 364). 1 = The MSCAN08 timer signal output is connected to the Timer Interface Module B Channel 0. 0 = The port is connected to the timer input. SLPAK -- Sleep Mode Acknowledge This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a handshake for the sleep mode request (see MSCAN08 Sleep Mode on page 361). If the MSCAN08 detects bus activity while in Sleep mode, it clears the flag. 1 = Sleep - MSCAN08 in internal sleep mode 0 = Wakeup - MSCAN08 is not in Sleep mode
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 377
MSCAN08 Controller (MSCAN08)
SLPRQ -- Sleep Request, Go to Internal Sleep Mode This flag requests the MSCAN08 to go into an internal power-saving mode (see MSCAN08 Sleep Mode on page 361). 1 = Sleep -- The MSCAN08 will go into internal sleep mode. 0 = Wakeup -- The MSCAN08 will function normally. SFTRES -- Soft Reset When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing transmission or reception is aborted and synchronization to the bus is lost. The following registers enter and stay in their hard reset state: CMCR0, CRFLG, CRIER, CTFLG, and CTCR. The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0-3, and CIDMR0-3 can only be written by the CPU when the MSCAN08 is in soft reset state. The values of the error counters are not affected by soft reset. When this bit is cleared by the CPU, the MSCAN08 tries to synchronize to the CAN bus. If the MSCAN08 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the MSCAN08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits. Clearing SFTRES and writing to other bits in CMCR0 must be in separate instructions. 1 = MSCAN08 in soft reset state 0 = Normal operation
Advance Information 378 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
21.14.2 MSCAN08 Module Control Register 1
Address:
$0501 Bit 7 6 0 5 0 4 0 3 0 2 LOOPB 0 1 WUPM 0 Bit 0 CLKSRC 0
Read: Write: Reset:
0
0
0
0
0
0
= Unimplemented
Figure 21-16. Module Control Register (CMCR1) LOOPB -- Loop Back Self-Test Mode When this bit is set, the MSCAN08 performs an internal loop back which can be used for self-test operation: the bit stream output of the transmitter is fed back to the receiver internally. The RxCAN input pin is ignored and the TxCAN output goes to the recessive state (logic `1'). The MSCAN08 behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state the MSCAN08 ignores the bit sent during the ACK slot of the CAN frame Acknowledge field to insure proper reception of its own message. Both transmit and receive interrupt are generated. 1 = Activate loop back self-test mode 0 = Normal operation WUPM -- Wakeup Mode This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from spurious wakeups (see Programmable Wakeup Function on page 364). 1 = MSCAN08 will wake up the CPU only in cases of a dominant pulse on the bus which has a length of at least twup. 0 = MSCAN08 will wake up the CPU after any recessive to dominant edge on the CAN bus.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 379
MSCAN08 Controller (MSCAN08)
CLKSRC -- Clock Source This flag defines which clock source the MSCAN08 module is driven from (see Clock System on page 364). 1 = The MSCAN08 clock source is CGMOUT (see Figure 21-7). 0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 21-7).
NOTE:
The CMCR1 register can be written only if the SFTRES bit in the MSCAN08 module control register is set
21.14.3 MSCAN08 Bus Timing Register 0
Address: $0502 Bit 7 Read: Write: Reset: SJW1 0 6 SJW0 0 5 BRP5 0 4 BRP4 0 3 BRP3 0 2 BRP2 0 1 BRP1 0 Bit 0 BRP0 0
Figure 21-17. Bus Timing Register 0 (CBTR0) SJW1 and SJW0 -- Synchronization Jump Width The synchronization jump width (SJW) defines the maximum number of time quanta (Tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus (see Table 21-6). Table 21-6. Synchronization Jump Width
SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq cycle 2 Tq cycle 3 Tq cycle 4 Tq cycle
Advance Information 380 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
BRP5-BRP0 -- Baud Rate Prescaler These bits determine the time quanta (Tq) clock, which is used to build up the individual bit timing, according toTable 21-7. Table 21-7. Baud Rate Prescaler
BRP5 0 0 0 0 BRP4 0 0 0 0 BRP3 0 0 0 0 BRP2 0 0 0 0 BRP1 0 0 1 1 BRP0 0 1 0 1 Prescaler Value (P) 1 2 3 4
: :
1
: :
1
: :
1
: :
1
: :
1
: :
1
: :
64
NOTE:
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08 module control register is set.
21.14.4 MSCAN08 Bus Timing Register 1
Address: $0503 Bit 7 Read: SAMP Write: Reset: 0 0 0 0 0 0 0 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 6 5 4 3 2 1 Bit 0
Figure 21-18. Bus Timing Register 1 (CBTR1) SAMP -- Sampling This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit. 1 = Three samples per bit(1) 0 = One sample per bit
1. In this case PHASE_SEG1 must be at least 2 time quanta.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 381
MSCAN08 Controller (MSCAN08)
TSEG22-TSEG10 -- Time Segment Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 21-9. Table 21-8. Time Segment Values
TSEG13 0 0 0 0 TSEG12 0 0 0 0 TSEG11 0 0 1 1 TSEG10 0 1 0 1 Time Segment 1 1 Tq Cycle(1) 2 Tq Cycles(1) 3Tq Cycles(1) 4 Tq Cycles TSEG22 0 0 TSEG21 0 0 TSEG20 0 1 Time Segment 2 1 Tq Cycle(1) 2 Tq Cycles
. .
1
. .
1
. .
1
. .
8Tq Cycles
. .
1
. .
1
. .
1
. .
1
. .
16 Tq Cycles
1. This setting is not valid. Please refer to Table 21-4 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit as shown in Table 21-9).
Bit time=
Pres value * number of Time Quanta fMSCANCLK
NOTE:
The CBTR1 register can only be written if the SFTRES bit in the MSCAN08 module control register is set.
Advance Information 382 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
21.14.5 MSCAN08 Receiver Flag Register (CRFLG) All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. A flag can be cleared only when the condition which caused the setting is valid no more. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the CRIER register. A hard or soft reset will clear the register.
Address: $0504 Bit 7 Read: WUPIF Write: Reset: 0 0 0 0 0 0 0 0 RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF 6 5 4 3 2 1 Bit 0
Figure 21-19. Receiver Flag Register (CRFLG) WUPIF -- Wakeup Interrupt Flag If the MSCAN08 detects bus activity while in Sleep mode, it sets the WUPIF flag. If not masked, a wake-up interrupt is pending while this flag is set. 1 = MSCAN08 has detected activity on the bus and requested wake-up. 0 = No wake-up interrupt has occurred. RWRNIF -- Receiver Warning Interrupt Flag This flag is set when the MSCAN08 goes into warning status due to the receive error counter (REC) exceeding 96 and neither one of the Error Interrupt flags or the Bus-off Interrupt flag is set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into receiver warning status. 0 = No receiver warning status has been reached.
1. Condition to set the flag: RWRNIF = (96 REC) & RERRIF & TERRIF & BOFFIF
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 383
MSCAN08 Controller (MSCAN08)
TWRNIF -- Transmitter Warning Interrupt Flag This flag is set when the MSCAN08 goes into warning status due to the transmit error counter (TEC) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into transmitter warning status. 0 = No transmitter warning status has been reached. RERRIF -- Receiver Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the receive error counter exceeding 127 and the bus-off interrupt flag is not set(2). If not masked, an Error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into receiver error passive status. 0 = No receiver error passive status has been reached. TERRIF -- Transmitter Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the Transmit Error counter exceeding 127 and the Bus-off interrupt flag is not set(3). If not masked, an Error interrupt is pending while this flag is set. 1 = MSCAN08 went into transmit error passive status. 0 = No transmit error passive status has been reached. BOFFIF -- Bus-Off Interrupt Flag This flag is set when the MSCAN08 goes into bus-off status, due to the transmit error counter exceeding 255. It cannot be cleared before the MSCAN08 has monitored 128 times 11 consecutive `recessive' bits on the bus. If not masked, an Error interrupt is pending while this flag is set. 1 = MSCAN08has gone into bus-off status. 0 = No bus-off status has bee reached.
1. Condition to set the flag: TWRNIF = (96 TEC) & RERRIF & TERRIF & BOFFIF 2. Condition to set the flag: RERRIF = (127 REC 255) & BOFFIF 3. Condition to set the flag: TERRIF = (128 TEC 255) & BOFFIF
Advance Information 384 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
OVRIF -- Overrun Interrupt Flag This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 1 = A data overrun has been detected since last clearing the flag. 0 = No data overrun has occurred. RXF -- Receive Buffer Full The RXF flag is set by the MSCAN08 when a new message is available in the foreground receive buffer. This flag indicates whether the buffer is loaded with a correctly received message. After the CPU has read that message from the receive buffer the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the exchange of the background receive buffer into the foreground buffer. If not masked, a receive interrupt is pending while this flag is set. 1 = The receive buffer is full. A new message is available. 0 = The receive buffer is released (not full).
NOTE: NOTE:
To ensure data integrity, no registers of the receive buffer shall be read while the RXF flag is cleared. The CRFLG register is held in the reset state when the SFTRES bit in CMCR0 is set.
21.14.6 MSCAN08 Receiver Interrupt Enable Register
Address:
$0505 Bit 7 6 RWRNIE 0 5 TWRNIE 0 4 RERRIE 0 3 TERRIE 0 2 BOFFIE 0 1 OVRIE 0 Bit 0 RXFIE 0
Read: WUPIE Write: Reset: 0
Figure 21-20. Receiver Interrupt Enable Register (CRIER) WUPIE -- Wakeup Interrupt Enable 1 = A wakeup event will result in a wakeup interrupt. 0 = No interrupt will be generated from this event.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08) Advance Information 385
MSCAN08 Controller (MSCAN08)
RWRNIE -- Receiver Warning Interrupt Enable 1 = A receiver warning status event will result in an error interrupt. 0 = No interrupt is generated from this event. TWRNIE -- Transmitter Warning Interrupt Enable 1 = A transmitter warning status event will result in an error interrupt. 0 = No interrupt is generated from this event. RERRIE -- Receiver Error Passive Interrupt Enable 1 = A receiver error passive status event will result in an error interrupt. 0 = No interrupt is generated from this event. TERRIE -- Transmitter Error Passive Interrupt Enable 1 = A transmitter error passive status event will result in an error interrupt. 0 = No interrupt is generated from this event. BOFFIE -- Bus-Off Interrupt Enable 1 = A bus-off event will result in an error interrupt. 0 = No interrupt is generated from this event. OVRIE -- Overrun Interrupt Enable 1 = An overrun event will result in an error interrupt. 0 = No interrupt is generated from this event. RXFIE -- Receiver Full Interrupt Enable 1 = A receive buffer full (successful message reception) event will result in a receive interrupt. 0 = No interrupt will be generated from this event.
NOTE:
The CRIER register is held in the reset state when the SFTRES bit in CMCR0 is set.
Advance Information 386 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
21.14.7 MSCAN08 Transmitter Flag Register The Abort Acknowledge flags are read only. The Transmitter Buffer Empty flags are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. The Transmitter Buffer Empty flags each have an associated interrupt enable bit in the CTCR register. A hard or soft reset will resets the register.
Address: $0506 Bit 7 Read: Write: Reset: 0 0 0 0 0 1 1 1 0 5 6 ABTAK2 5 ABTAK1 4 ABTAK0 3 0 TXE2 TXE1 TXE0 2 1 Bit 0
= Unimplemented
Figure 21-21. Transmitter Flag Register (CTFLG) ABTAK2-ABTAK0 -- Abort Acknowledge This flag acknowledges that a message has been aborted due to a pending abort request from the CPU. After a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the message has been aborted successfully or has been sent. The ABTAKx flag is cleared implicitly whenever the corresponding TXE flag is cleared. 1 = The message has been aborted. 0 = The message has not been aborted, thus has been sent out. TXE2-TXE0 -- Transmitter Empty This flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. The CPU must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. The MSCAN08 sets the flag after the message has been sent successfully. The flag is also set by the MSCAN08 when the transmission request was successfully
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 387
MSCAN08 Controller (MSCAN08)
aborted due to a pending abort request (see Transmit Buffer Priority Registers on page 374). If not masked, a receive interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx flag (ABTAK, see above). When a TXEx flag is set, the corresponding ABTRQx bit (ABTRQ, see MSCAN08 Transmitter Control Register) is cleared. 1 = The associated message buffer is empty (not scheduled). 0 = The associated message buffer is full (loaded with a message due for transmission).
NOTE: NOTE:
To ensure data integrity, no registers of the transmit buffers should be written to while the associated TXE flag is cleared. The CTFLG register is held in the reset state when the SFTRES bit in CMCR0 is set.
21.14.8 MSCAN08 Transmitter Control Register
Address:
$0507 Bit 7 6 ABTRQ2 5 ABTRQ1 0 4 ABTRQ0 0 0 3 0 TXEIE2 0 TXEIE1 0 TXEIE0 0 2 1 Bit 0
Read: Write: Reset:
0
0
0
= Unimplemented
Figure 21-22. Transmitter Control Register (CTCR) ABTRQ2-ABTRQ0 -- Abort Request The CPU sets an ABTRQx bit to request that an already scheduled message buffer (TXE = 0) be aborted. The MSCAN08 will grant the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted the associated TXE and the abort acknowledge flag (ABTAK) (see MSCAN08 Transmitter Flag Register on page
Advance Information 388 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
387) will be set and an TXE interrupt is generated if enabled. The CPU cannot reset ABTRQx. ABTRQx is cleared implicitly whenever the associated TXE flag is set. 1 = Abort request pending 0 = No abort request
NOTE:
The software must not clear one or more of the TXE flags in CTFLG and simultaneously set the respective ABTRQ bit(s). TXEIE2-TXEIE0 -- Transmitter Empty Interrupt Enable 1 = A transmitter empty (transmit buffer available for transmission) event results in a transmitter empty interrupt. 0 = No interrupt is generated from this event.
NOTE:
The CTCR register is held in the reset state when the SFTRES bit in CMCR0 is set.
21.14.9 MSCAN08 Identifier Acceptance Control Register
Address: $0508 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 IDAM1 IDAM0 5 4 3 0 2 0 1 IDHIT1 Bit 0 IDHIT0
= Unimplemented
Figure 21-23. Identifier Acceptance Control Register (CIDAC) IDAM1-IDAM0-- Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see Identifier Acceptance Filter on page 352). Table 21-9 summarizes the different settings. In "filter closed" mode no messages will be accepted so that the foreground buffer will never be reloaded.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 389
MSCAN08 Controller (MSCAN08)
Table 21-9. Identifier Acceptance Mode Settings
IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identifier Acceptance Mode Single 32-Bit Acceptance Filter Two 16-Bit Acceptance Filter Four 8-Bit Acceptance Filters Filter Closed
IDHIT1-IDHIT0-- Identifier Acceptance Hit Indicator The MSCAN08 sets these flags to indicate an identifier acceptance hit (see Identifier Acceptance Filter on page 352). Table 21-9 summarizes the different settings. Table 21-10. Identifier Acceptance Hit Indication
IDHIT1 0 0 1 1 IDHIT0 0 1 0 1 Identifier Acceptance Hit Filter 0 Hit Filter 1 Hit Filter 2 Hit Filter 3 Hit
The IDHIT indicators are always related to the message in the foreground buffer. When a message gets copied from the background to the foreground buffer, the indicators are updated as well.
NOTE:
The CIDAC register can be written only if the SFTRES bit in the CMCR0 is set.
Advance Information 390 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
21.14.10 MSCAN08 Receive Error Counter
Address:
$050E Bit 7 6 RXERR6 5 RXERR5 4 RXERR4 3 RXERR3 2 RXERR2 1 RXERR1 Bit 0 RXERR0
Read: RXERR7 Write: Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 21-24. Receiver Error Counter (CRXERR) This register reflects the status of the MSCAN08 receive error counter. The register is read only.
21.14.11 MSCAN08 Transmit Error Counter
Address:
$050F Bit 7 6 TXERR6 5 TXERR5 4 TXERR4 3 TXERR3 2 TXERR2 1 TXERR1 Bit 0 TXERR0
Read: TXERR7 Write: Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 21-25. Transmit Error Counter (CTXERR) This register reflects the status of the MSCAN08 transmit error counter. The register is read only.
NOTE:
Both error counters may only be read when in Sleep or Soft Reset mode.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08)
Advance Information 391
MSCAN08 Controller (MSCAN08)
21.14.12 MSCAN08 Identifier Acceptance Registers On reception each message is written into the background receive buffer. The CPU is only signalled to read the message, however, if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming messages in a bit by bit manner. For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only the first two (CIDMR0/1 and CIDAR0/1) are applied.
CIDAR0 Address: $0510 Bit 7 Read: Write: Reset: CIDAR1 Address: $0511 Bit 7 Read: Write: Reset: CIDAR2 Address: $0512 Bit 7 Read: Write: Reset: CIDAR3 Address: $0513 Bit 7 Read: Write: Reset: AC7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0 AC7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0 AC7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0 AC7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0
Unaffected by Reset
Unaffected by Reset
Unaffected by Reset
Unaffected by Reset
Figure 21-26. Identifier Acceptance Registers (CIDAR0-CIDAR3)
Advance Information 392 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
AC7-AC0 -- Acceptance Code Bits AC7-AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
NOTE:
The CIDAR0-3 registers can be written only if the SFTRES bit in CMCR0 is set
21.14.13 MSCAN08 Identifier Mask Registers (CIDMR0-3) The identifier mask registers specify which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. For standard identifiers it is required to program the last three bits (AM2AM0) in the mask register CIDMR1 to `don't care'.
CIDMRO Read: Write: Reset: CIDMR1 Read: Write: Reset: CIDMR2 Read: Write: Reset: CIDMR3 Read: Write: Reset: Address: $0517 Bit 7 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 Address: $0516 Bit 7 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 Address: $0515 Bit 7 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 Address: $0514 Bit 7 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0
Unaffected by Reset
Unaffected by Reset
Unaffected by Reset
Unaffected by Reset
Figure 21-27. Identifier Mask Registers (CIDMR0-CIDMR3)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA MSCAN08 Controller (MSCAN08) Advance Information 393
MSCAN08 Controller (MSCAN08)
AM7-AM0 -- Acceptance Mask Bits If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match will be detected. The message will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register will not affect whether or not the message is accepted. 1 = Ignore corresponding acceptance code register bit. 0 = Match corresponding acceptance code register and identifier bits.
NOTE:
The CIDMR0-3 registers can be written only if the SFTRES bit in the CMCR0 is set
Advance Information 394 MSCAN08 Controller (MSCAN08)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 22. Keyboard Module (KBD)
22.1 Contents
22.2 22.3 22.4 22.5 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .396 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 22.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 22.7 Keyboard Module During Break Interrupts . . . . . . . . . . . .400
22.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 22.8.1 Keyboard Status and Control Register . . . . . . . . . . . . . 401 22.8.2 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . 402
22.2 Introduction
The keyboard interrupt module (KBD) provides five independently maskable external interrupt pins.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Keyboard Module (KBD)
Advance Information 395
Keyboard Module (KBD) 22.3 Features
KBD features include: * * * * * Five Keyboard Interrupt Pins with Separate Keyboard Interrupt Enable Bits and One Keyboard Interrupt Mask Hysteresis Buffers Programmable Edge-Only or Edge- and Level- Interrupt Sensitivity Automatic Interrupt Acknowledge Exit from Low-Power Modes
22.4 Functional Description
Writing to the KBIE4-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port G or port H pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low.
*
Advance Information 396 Keyboard Module (KBD)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
MOTOROLA Keyboard Module (KBD) 397
MC68HC08AZ60A -- Rev 0.0 Advance Information
INTERNAL BUS
KBD0 VDD TO PULLUP ENABLE KB0IE . KBD4 . . D CLR Q
ACKK RESET
VECTOR FETCH DECODER KEYF SYNCHRONIZER
CK KEYBOARD INTERRUPT REQUEST
KEYBOARD INTERRUPT FF
IMASKK
TO PULLUP ENABLE KB4IE
MODEK
Figure 22-1. Keyboard Module Block Diagram
Register Name Read: Keyboard Status and Control RegWrite: ister (KBSCR) Reset: Read: Keyboard Interrupt Enable RegisWrite: ter (KBIER) Reset: Bit 7 0 0 0 0 6 0 0 0 0 5 0 0 0 0 4 0 0 KBIE4 0 3 KEYF 0 KBIE3 0 2 0 ACKK 0 KBIE2 0 1 IMASKK 0 KBIE1 0 Bit 0 MODEK 0 KBIE0 0
= Unimplemented
Figure 22-2. I/O Register Summary
Keyboard Module (KBD) Functional Description
Table 22-1. I/O Register Address Summary
Register Address KBSCR $001A KBIER $001B
Keyboard Module (KBD)
If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFDE and $FFDF. Return of all enabled keyboard interrupt pins to logic 1. As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
*
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling edgesensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register.
Advance Information 398 Keyboard Module (KBD) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Keyboard Module (KBD) Keyboard Initialization
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.
22.5 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRG bits in data direction register G. 2. Configure the keyboard pins as outputs by setting the appropriate DDRH bits in data direction register H. 3. Write logic 1s to the appropriate port G and port H data register bits. 4. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Keyboard Module (KBD)
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Keyboard Module (KBD) 22.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
22.6.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
22.6.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
22.7 Keyboard Module During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Break Module on page 171. To allow software to clear the KEYF bit during a break interrupt, write a logic 1 to the BCFE bit. If KEYF is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the KEYF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0, writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. See Keyboard Status and Control Register on page 401.
Advance Information 400 Keyboard Module (KBD)
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Keyboard Module (KBD) I/O Registers
22.8 I/O Registers
The following registers control and monitor operation of the keyboard module: * * Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER)
22.8.1 Keyboard Status and Control Register The keyboard status and control register: * * * * Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
Address: $001A Bit 7 Read: Write: Reset: 0 0 0 0 0 0 6 0 5 0 4 0 3 KEYF 2 0 IMASKK ACKK 0 0 0 MODEK 1 Bit 0
= Unimplemented
Figure 22-3. Keyboard Status and Control Register (KBSCR) Bits 7-4 -- Not used These read-only bits always read as logic 0s. KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending
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Keyboard Module (KBD)
ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK -- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
22.8.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port G and each port H pin to operate as a keyboard interrupt pin.
Address: $001B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 4 3 2 1 Bit 0
= Unimplemented
Figure 22-4. Keyboard Interrupt Enable Register (KBIER) KBIE4-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = Port pin enabled as keyboard interrupt pin 0 = Port pin not enabled as keyboard interrupt pin
Advance Information 402 Keyboard Module (KBD) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 23. Timer Interface Module A (TIMA)
23.1 Contents
23.2 23.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
23.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .407 23.4.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . 408 23.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 23.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 23.4.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . 409 23.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . .410 23.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . .412 23.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . 413 23.4.4.2 Buffered PWM Signal Generation. . . . . . . . . . . . . . . . 414 23.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 23.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
23.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 23.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 23.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 23.7 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 418
23.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 23.8.1 TIMA Clock Pin (PTD6/ATD14/TACLK) . . . . . . . . . . . . . . 418 23.8.2 TIMA Channel I/O Pins (PTF3-PTF0/TACH2 and PTE3/TACH1-PTE2/TACH0) . . . . . . . . . . . . . . . . . . . . . . 419 23.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 23.9.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . 420 23.9.2 TIMA Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . 422 23.9.3 TIMA Counter Modulo Registers. . . . . . . . . . . . . . . . . . . 423 23.9.4 TIMA Channel Status and Control Registers. . . . . . . . . 424 23.9.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . 429
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) Advance Information 403
Timer Interface Module A (TIMA) 23.2 Introduction
This section describes the timer interface module (TIMA). The TIMA is a 6-channel timer that provides a timing reference with input capture, output compare and pulse-width-modulation functions. Figure 23-1 is a block diagram of the TIMA. For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer Reference Manual, TIM08RM/AD.
23.3 Features
Features of the TIMA include: * Six Input Capture/Output Compare Channels - Rising-Edge, Falling-Edge or Any-Edge Input Capture Trigger - Set, Clear or Toggle Output Compare Action * * Buffered and Unbuffered Pulse Width Modulation (PWM) Signal Generation Programmable TIMA Clock Input - 7 Frequency Internal Bus Clock Prescaler Selection - External TIMA Clock Input (4 MHz Maximum Frequency) * * * Free-Running or Modulo Up-Count Operation Toggle Any Channel Pin on Overflow TIMA Counter Stop and Reset Bits
Advance Information 404 Timer Interface Module A (TIMA)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Timer Interface Module A (TIMA) Features
PTD6/ATD14/TACLK INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER
TCLK PRESCALER SELECT PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CHANNEL 2 16-BIT COMPARATOR TCH2H:TCH2L 16-BIT LATCH MS2A CHANNEL 3 16-BIT COMPARATOR TCH3H:TCH3L 16-BIT LATCH MS3A CHANNEL 4 16-BIT COMPARATOR TCH4H:TCH4L 16-BIT LATCH MS4A CHANNEL 5 16-BIT COMPARATOR TCH5H:TCH5L 16-BIT LATCH MS5A CH5IE CH5F ELS5B ELS5A MS4B CH4IE TOV5 CH5MAX CH4F ELS4B ELS4A CH3IE TOV4 CH5MAX CH3F ELS3B ELS3A MS2B CH2IE TOV3 CH3MAX CH2F ELS2B ELS2A CH1IE TOV2 CH2MAX CH1F ELS1B ELS1A MS0B CH0IE TOV1 CH1MAX CH0F ELS0B ELS0A TOV0 CH0MAX
PTE2 LOGIC INTERRUPT LOGIC
PTE2/TACH0
PTE3 LOGIC INTERRUPT LOGIC
PTE3/TACH1
PTF0 LOGIC INTERRUPT LOGIC
PTF0/TACH2
PTF1 LOGIC INTERRUPT LOGIC
PTF1/TACH3
PTF2 LOGIC INTERRUPT LOGIC
PTF2/TACH4
PTF3 LOGIC INTERRUPT LOGIC
PTF3/TACH5
Figure 23-1. TIMA Block Diagram
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) Advance Information 405
Timer Interface Module A (TIMA)
Figure 23-2. TIMA I/O Register Summary
Addr. $0020 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F $0030 $0031 Register Name TIMA Status/Control Register (TASC) TIMA Counter Register High (TACNTH) TIMA Counter Register Low (TACNTL) R: W: R: W: R: W: Bit 7 TOF 0 Bit 15 R Bit 7 R Bit 15 Bit 7 CH0F 0 Bit 15 Bit 7 CH1F 0 Bit 15 Bit 7 CH2F 0 Bit 15 Bit 7 CH3F 0 Bit 15 Bit 7 6 TOIE 14 R 6 R 14 6 CH0IE 14 6 CH1IE 14 6 CH2IE 14 6 CH3IE 14 6 5 TSTOP 13 R 5 R 13 5 MS0B 13 5 0 R 13 5 MS2B 13 5 0 R 13 5 4 0 TRST 12 R 4 R 12 4 MS0A 12 4 MS1A 12 4 MS2A 12 4 MS3A 12 4 3 0 R 11 R 3 R 11 3 ELS0B 11 3 ELS1B 11 3 ELS2B 11 3 ELS3B 11 3 2 PS2 10 R 2 R 10 2 ELS0A 10 2 ELS1A 10 2 ELS2A 10 2 ELS3A 10 2 1 PS1 9 R 1 R 9 1 TOV0 9 1 TOV1 9 1 TOV2 9 1 TOV3 9 1 Bit 0 PS0 Bit 8 R Bit 0 R Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0 CH2MAX Bit 8 Bit 0 CH3MAX Bit 8 Bit 0
TIMA Counter Modulo Reg. High R: (TAMODH) W: TIMA Counter Modulo Reg. Low R: (TAMODL) W: TIMA Ch. 0 Status/Control Register R: (TASC0) W: TIMA Ch. 0 Register High (TACH0H) TIMA Ch. 0 Register Low (TACH0L) R: W: R: W:
TIMA Ch. 1 Status/Control Register R: (TASC1) W: TIMA Ch. 1 Register High (TACH1H) TIMA Ch. 1 Register Low (TACH1L) R: W: R: W:
TIMA Ch. 2 Status/Control Register R: (TASC2) W: TIMA Ch. 2 Register High (TACH2H) TIMA Ch. 2 Register Low (TACH2L) R: W: R: W:
TIMA Ch. 3 Status/Control Register R: (TASC3) W: TIMA Ch. 3 Register High (TACH3H) TIMA Ch. 3 Register Low (TACH3L) R: W: R: W:
Advance Information 406 Timer Interface Module A (TIMA)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Timer Interface Module A (TIMA) Functional Description
Figure 23-2. TIMA I/O Register Summary
Addr. $0032 $0033 $0034 $0035 $0036 $0037 Register Name TIMA Ch. 4 Status/Control Register R: (TASC4) W: TIMA Ch. 4 Register High (TACH4H) TIMA Ch. 4 Register Low (TACH4L) R: W: R: W: Bit 7 CH4F 0 Bit 15 Bit 7 CH5F 0 Bit 15 Bit 7 6 CH4IE 14 6 CH5IE 14 6 5 MS4B 13 5 0 R 13 5 4 MS4A 12 4 MS5A 12 4 3 ELS4B 11 3 ELS5B 11 3 2 ELS4A 10 2 ELS5A 10 2 1 TOV4 9 1 TOV5 9 1 Bit 0 CH4MAX Bit 8 Bit 0 CH5MAX Bit 8 Bit 0
TIMA Ch. 5 Status/Control Register R: (TASC5) W: TIMA Ch. 5 Register High (TACH5H) TIMA Ch. 5 Register Low (TACH5L) R: W: R: W:
R
= Reserved
23.4 Functional Description
Figure 23-1 shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing reference for the input capture and output compare functions. The TIMA counter modulo registers, TAMODH-TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter value at any time without affecting the counting sequence. The six TIMA channels are programmable independently as input capture or output compare channels.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA)
Advance Information 407
Timer Interface Module A (TIMA)
23.4.1 TIMA Counter Prescaler The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTD6/ATD14/TACLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source.
23.4.2 Input Capture An input capture function has three basic parts: edge select logic, an input capture latch and a 16-bit counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The polarity of the active edge is programmable. The level transition which triggers the counter transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0 through TASC5 control registers with x referring to the active channel number). When an active edge occurs on the pin of an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel registers, TACHxH-TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit. The free-running counter contents are transferred to the TIMA channel register (TACHxH-TACHxL see TIMA Channel Registers on page 429) on each proper signal transition regardless of whether the TIMA channel flag (CH0F-CH5F in TASC0-TASC5 registers) is set or clear. When the status flag is set, a CPU interrupt is generated if enabled. The value of the count latched or "captured" is the time of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. However, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost. By recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are
Advance Information 408 Timer Interface Module A (TIMA) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Timer Interface Module A (TIMA) Functional Description
captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the overflows at the 16-bit module counter to extend its range. Another use for the input capture function is to establish a time reference. In this case, an input capture function is used in conjunction with an output compare function. For example, to activate an output signal a specified number of clock cycles after detecting an input event (edge), use the input capture function to record the time at which the edge occurred. A number corresponding to the desired delay is added to this captured value and stored to an output compare register (see TIMA Channel Registers on page 429). Because both input captures and output compares are referenced to the same 16-bit modulo counter, the delay can be controlled to the resolution of the counter independent of software latencies. Reset does not affect the contents of the TIMA channel register (TACHxH-TACHxL).
23.4.3 Output Compare With the output compare function, the TIMA can generate a periodic pulse with a programmable polarity, duration and frequency. When the counter reaches the value in the registers of an output compare channel, the TIMA can set, clear or toggle the channel pin. Output compares can generate TIMA CPU interrupt requests. 23.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in Output Compare on page 409. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also,
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA) Advance Information 409
Timer Interface Module A (TIMA)
using a TIMA overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMA may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
*
23.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The output compare value in the TIMA channel 0 registers initially controls the output on the PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the output are the ones written to last. TASC0 controls and monitors the buffered output compare function and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin.
Advance Information 410 Timer Interface Module A (TIMA)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Timer Interface Module A (TIMA) Functional Description
Channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel 3. The output compare value in the TIMA channel 2 registers initially controls the output on the PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (2 or 3) that control the output are the ones written to last. TASC2 controls and monitors the buffered output compare function, and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin. Channels 4 and 5 can be linked to form a buffered output compare channel whose output appears on the PTF2 pin. The TIMA channel registers of the linked pair alternately control the output. Setting the MS4B bit in TIMA channel 4 status and control register (TASC4) links channel 4 and channel 5. The output compare value in the TIMA channel 4 registers initially controls the output on the PTF2 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (4 or 5) that control the output are the ones written to last. TASC4 controls and monitors the buffered output compare function and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is set, the channel 5 pin, PTF3, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA)
Advance Information 411
Timer Interface Module A (TIMA)
23.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 23-3 shows, the output compare value in the TIMA channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to set the pin if the state of the PWM pulse is logic 0.
OVERFLOW PERIOD OVERFLOW OVERFLOW
PULSE WIDTH PTEx/TCHx
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 23-3. PWM Period and Pulse Width The value in the TIMA counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIMA counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000 (see TIMA Status and Control Register on page 420). The value in the TIMA channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers produces a duty cycle of 128/256 or 50%.
Advance Information 412 Timer Interface Module A (TIMA) MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Timer Interface Module A (TIMA) Functional Description
23.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in Pulse Width Modulation (PWM) on page 412. The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIMA channel registers. An unsynchronized write to the TIMA channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIMA overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIMA may pass the new value before it is written to the TIMA channel registers. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Timer Interface Module A (TIMA)
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Timer Interface Module A (TIMA)
23.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered PWM function and TIMA channel 1 status and control register (TASC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TACH1, is available as a general-purpose I/O pin. Channels 2 and 3 can be linked to form a buffered PWM channel whose output appears on the PTF0/TACH2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS2B bit in TIMA channel 2 status and control register (TASC2) links channel 2 and channel 3. The TIMA channel 2 registers initially control the pulse width on the PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the TIMA channel 3 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (2 or 3) that control the pulse width are the ones written to last. TASC2 controls and monitors the buffered PWM function and TIMA channel 3 status and control register (TASC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a general-purpose I/O pin. Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the PTF2 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output. Setting the MS4B bit in TIMA channel 4 status and control register (TASC4) links channel 4 and channel 5. The TIMA channel 4 registers
Advance Information 414 Timer Interface Module A (TIMA)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Timer Interface Module A (TIMA) Functional Description
initially control the pulse width on the PTF2 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (4 or 5) that control the pulse width are the ones written to last. TASC4 controls and monitors the buffered PWM function and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is set, the channel 5 pin, PTF3, is available as a general-purpose I/O pin.
NOTE:
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
23.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIMA status and control register (TASC): a. Stop the TIMA counter and prescaler by setting the TIMA stop bit, TSTOP. b. Reset the TIMA counter and prescaler by setting the TIMA reset bit, TRST. 2. In the TIMA counter modulo registers (TAMODH-TAMODL) write the value for the required PWM period. 3. In the TIMA channel x registers (TACHxH-TACHxL) write the value for the required pulse width. 4. In TIMA channel x status and control register (TASCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB-MSxA (see Table 23-2). b. Write 1 to the toggle-on-overflow bit, TOVx.
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Timer Interface Module A (TIMA)
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB-ELSxA. The output action on compare must force the output to the complement of the pulse width level (see Table 23-2).
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIMA status control register (TASC) clear the TIMA stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA channel 0 registers (TACH0H-TACH0L) initially control the buffered PWM output. TIMA status control register 0 (TASC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIMA channel 2 registers (TACH2H-TACH2L) initially control the buffered PWM output. TIMA status control register 2 (TASC2) controls and monitors the PWM signal from the linked channels. MS2B takes priority over MS2A. Setting MS4B links channels 4 and 5 and configures them for buffered PWM operation. The TIMA channel 4 registers (TACH4H-TACH4L) initially control the buffered PWM output. TIMA status control register 4 (TASC4) controls and monitors the PWM signal from the linked channels. MS4B takes priority over MS4A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMA overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output (see TIMA Channel Status and Control Registers on page 424).
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Timer Interface Module A (TIMA) Interrupts
23.5 Interrupts
The following TIMA sources can generate interrupt requests: * TIMA overflow flag (TOF) -- The TOF bit is set when the TIMA counter reaches the modulo value programmed in the TIMA counter modulo registers. The TIMA overflow interrupt enable bit, TOIE, enables TIMA overflow CPU interrupt requests. TOF and TOIE are in the TIMA status and control register. TIMA channel flags (CH5F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIMA CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE.
*
23.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
23.6.1 Wait Mode The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of wait mode. If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA before executing the WAIT instruction.
23.6.2 Stop Mode The TIMA is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop mode.
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Timer Interface Module A (TIMA) 23.7 TIMA During Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state (see SIM Break Flag Control Register (SBFCR) on page 137). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
23.8 I/O Signals
Port D shares one of its pins with the TIMA. Port E shares two of its pins with the TIMA and port F shares four of its pins with the TIMA. PTD6/ATD14/TACLK is an external clock input to the TIMA prescaler. The six TIMA channel I/O pins are PTE2/TACH0, PTE3/TACH1, PTF0/TACH2, PTF1/TACH3, PTF2, and PTF3.
23.8.1 TIMA Clock Pin (PTD6/ATD14/TACLK) PTD6/ATD14/TACLK is an external clock input that can be the clock source for the TIMA counter instead of the prescaled internal bus clock. Select the PTD6/ATD14/TACLK input by writing logic 1s to the three
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Timer Interface Module A (TIMA) I/O Registers
prescaler select bits, PS[2:0] (see TIMA Status and Control Register). The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 ------------------------------------ + t SU bus frequency The maximum TCLK frequency is the least: 4 MHz or bus frequency / 2. PTD6/ATD14/TACLK is available as a general-purpose I/O pin or ADC channel when not used as the TIMA clock input. When the PTD6/ATD14/TACLK pin is the TIMA clock input, it is an input regardless of the state of the DDRD6 bit in data direction register D.
23.8.2 TIMA Channel I/O Pins (PTF3-PTF0/TACH2 and PTE3/TACH1-PTE2/TACH0) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTE2/TACH0, PTF0/TACH2 and PTF2 can be configured as buffered output compare or buffered PWM pins.
23.9 I/O Registers
These I/O registers control and monitor TIMA operation: * * * * * TIMA status and control register (TASC) TIMA control registers (TACNTH-TACNTL) TIMA counter modulo registers (TAMODH-TAMODL) TIMA channel status and control registers (TASC0, TASC1, TASC2, TASC3, TASC4 and TASC5) TIMA channel registers (TACH0H-TACH0L, TACH1H-TACH1L, TACH2H-TACH2L, TACH3H-TACH3L, TACH4H-TACH4L and TACH5H-TACH5L)
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Timer Interface Module A (TIMA)
23.9.1 TIMA Status and Control Register The TIMA status and control register: * * * * *
Address:
Enables TIMA overflow interrupts Flags TIMA overflows Stops the TIMA counter Resets the TIMA counter Prescales the TIMA counter clock
$0020 Bit 7 6 TOIE 5 TSTOP TRST 0 = Reserved 1 0 R 0 0 0 0 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0
Read: Write: Reset:
TOF 0 0 R
Figure 23-4. TIMA Status and Control Register (TASC) TOF -- TIMA Overflow Flag Bit This read/write flag is set when the TIMA counter reaches the modulo value programmed in the TIMA counter modulo registers. Clear TOF by reading the TIMA status and control register when TOF is set and then writing a logic 0 to TOF. If another TIMA overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIMA counter has reached modulo value. 0 = TIMA counter has not reached modulo value. TOIE -- TIMA Overflow Interrupt Enable Bit This read/write bit enables TIMA overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMA overflow interrupts enabled 0 = TIMA overflow interrupts disabled
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Timer Interface Module A (TIMA) I/O Registers
TSTOP -- TIMA Stop Bit This read/write bit stops the TIMA counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMA counter until software clears the TSTOP bit. 1 = TIMA counter stopped 0 = TIMA counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIMA is required to exit wait mode. Also, when the TSTOP bit is set and input capture mode is enabled, input captures are inhibited until TSTOP is cleared. TRST -- TIMA Reset Bit Setting this write-only bit resets the TIMA counter and the TIMA prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIMA counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIMA counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select either the PTD6/ATD14/TACLK pin or one of the seven prescaler outputs as the input to the TIMA counter as Table 23-1 shows. Reset clears the PS[2:0] bits. Table 23-1. Prescaler Selection
PS[2:0] 000 001 010 011 100 101 110 111 TIMA Clock Source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 PTD6/ATD14/TACLK Advance Information Timer Interface Module A (TIMA) 421
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Timer Interface Module A (TIMA)
23.9.2 TIMA Counter Registers The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter. Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers.
NOTE:
If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by reading TACNTL before exiting the break interrupt. Otherwise, TACNTL retains the value latched during the break.
Register Name and Address TACNTH -- $0022 Bit 7 Read: Write: Reset: BIT 15 R 0 6 BIT 14 R 0 5 BIT 13 R 0 4 BIT 12 R 0 3 BIT 11 R 0 2 BIT 10 R 0 1 BIT 9 R 0 Bit 0 BIT 8 R 0
Register Name and Address TACNTL -- $0023 Bit 7 Read: Write: Reset: BIT 7 R 0 R 6 BIT 6 R 0 = Reserved 5 BIT 5 R 0 4 BIT 4 R 0 3 BIT 3 R 0 2 BIT 2 R 0 1 BIT 1 R 0 Bit 0 BIT 0 R 0
Figure 23-5. TIMA Counter Registers (TACNTH and TACNTL)
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Timer Interface Module A (TIMA) I/O Registers
23.9.3 TIMA Counter Modulo Registers The read/write TIMA modulo registers contain the modulo value for the TIMA counter. When the TIMA counter reaches the modulo value, the overflow flag (TOF) becomes set and the TIMA counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TAMODH) inhibits the TOF bit and overflow interrupts until the low byte (TAMODL) is written. Reset sets the TIMA counter modulo registers.
Register Name and Address TAMODH -- $0024 Bit 7 Read: BIT 15 Write: Reset: 1 1 1 1 1 1 1 1 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 6 5 4 3 2 1 Bit 0
Register Name and Address TAMODL -- $0025 Bit 7 Read: BIT 7 Write: Reset: 1 1 1 1 1 1 1 1 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 6 5 4 3 2 1 Bit 0
Figure 23-6. TIMA Counter Modulo Registers (TAMODH and TAMODL)
NOTE:
Reset the TIMA counter before writing to the TIMA counter modulo registers.
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23.9.4 TIMA Channel Status and Control Registers Each of the TIMA channel status and control registers: * * * * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare or PWM operation Selects high, low or toggling output on output compare Selects rising edge, falling edge or any edge as the active input capture trigger Selects output toggling on TIMA overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
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Timer Interface Module A (TIMA) I/O Registers
Register Name and Address TASC0 -- $0026 Bit 7 Read: Write: Reset: CH0F 0 0 6 CH0IE 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0
Register Name and Address TASC1 -- $0029 Bit 7 Read: Write: Reset: CH1F 0 0 R Bit 7 Read: Write: Reset: CH2F 0 0 6 CH1IE 0 = Reserved 6 CH2IE 0 5 MS2B 0 4 MS2A 0 3 ELS2B 0 2 ELS2A 0 1 TOV2 0 Bit 0 CH2MAX 0 5 0 R 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0
Register Name and Address TASC2 -- $002C
Register Name and Address TASC3 -- $002F Bit 7 Read: Write: Reset: CH3F 0 0 6 CH3IE 0 5 0 R 0 4 MS3A 0 3 ELS3B 0 2 ELS3A 0 1 TOV3 0 Bit 0 CH3MAX 0
Register Name and Address TASC4 -- $0032 Bit 7 Read: Write: Reset: CH4F 0 0 6 CH4IE 0 5 MS4B 0 4 MS4A 0 3 ELS4B 0 2 ELS4A 0 1 TOV4 0 Bit 0 CH4MAX 0
Register Name and Address TASC5 -- $0035 Bit 7 Read: Write: Reset: CH5F 0 0 R 6 CH5IE 0 = Reserved 5 0 R 0 4 MS5A 0 3 ELS5B 0 2 ELS5A 0 1 TOV5 0 Bit 0 CH5MAX 0
Figure 23-7. TIMA Channel Status and Control Registers (TASC0-TASC5)
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Timer Interface Module A (TIMA)
CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIMA counter registers matches the value in the TIMA channel x registers. When CHxIE = 1, clear CHxF by reading TIMA channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIMA CPU interrupts on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA channel 0, TIMA channel 2 and TIMA channel 4 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TACH1 pin to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts TACH3 pin to general-purpose I/O. Setting MS4B disables the channel 5 status and control register and reverts TACH5 pin to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled
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Timer Interface Module A (TIMA) I/O Registers
MSxA -- Mode Select Bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 23-2. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TACHx pin once PWM, output compare mode or input capture mode is enabled. See Table 23-2. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMA status and control register (TASC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F and pin PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits and becomes transparent to the respective pin when PWM, input capture mode or output compare operation mode is enabled. Table 23-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
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Timer Interface Module A (TIMA)
Table 23-2. Mode, Edge, and Level Selection
MSxB:MSxA X0 ELSxB:ELSxA 00 Output Preset X1 00 00 00 01 01 01 1X 1X 1X 00 01 10 11 01 10 11 01 10 11 Output Compare or PWM Buffered Output Compare or Buffered PWM Input Capture Mode Configuration Pin under Port Control; Initialize Timer Output Level High Pin under Port Control; Initialize Timer Output Level Low Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare
NOTE:
Before enabling a TIMA channel register for input capture operation, make sure that the PTEx/TACHx pin or PTFx/TACHx pin is stable for at least two bus clocks. TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIMA counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIMA counter overflow. 0 = Channel x pin does not toggle on TIMA counter overflow.
NOTE:
When TOVx is set, a TIMA counter overflow takes precedence over a channel x output compare if both occur at the same time.
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Timer Interface Module A (TIMA) I/O Registers
CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 23-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
PERIOD
PTEx/TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 23-8. CHxMAX Latency
23.9.5 TIMA Channel Registers These read/write registers contain the captured TIMA counter value of the input capture function or the output compare value of the output compare function. The state of the TIMA channel registers after reset is unknown. In input capture mode (MSxB-MSxA = 0:0) reading the high byte of the TIMA channel x registers (TACHxH) inhibits input captures until the low byte (TACHxL) is read. In output compare mode (MSxB-MSxA 0:0) writing to the high byte of the TIMA channel x registers (TACHxH) inhibits output compares and the CHxF bit until the low byte (TACHxL) is written.
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Register Name and Address TACH0H -- $0027 Bit 7 Read: Write: Reset: Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Indeterminate after Reset
Register Name and Address TACH0L -- $0028 Bit 7 Read: Write: Reset: Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
Indeterminate after Reset
Register Name and Address TACH1H -- $002A Bit 7 Read: Write: Reset: Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Indeterminate after Reset
Register Name and Address TACH1L -- $002B Bit 7 Read: Write: Reset: Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
Indeterminate after Reset
Register Name and Address TACH2H -- $002D Bit 7 Read: Write: Reset: Bit 7 Read: Write: Reset: Bit 7 6 Bit 6 5 Bit 5 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Indeterminate after Reset 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
Register Name and Address TACH2L -- $002E
Indeterminate after Reset
Figure 23-9. TIMA Channel Registers (TACH0H/L-TACH5H/L) (Sheet 1 of 2)
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Timer Interface Module A (TIMA) I/O Registers
Register Name and Address TACH3H -- $0030 Bit 7 Read: Write: Reset: Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Indeterminate after Reset
Register Name and Address TACH3L -- $0031 Bit 7 Read: Write: Reset: Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
Indeterminate after Reset
Register Name and Address TACH4H -- $0033 Bit 7 Read: Write: Reset: Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Indeterminate after Reset
Register Name and Address TACH4L -- $0034 Bit 7 Read: Write: Reset: Bit 7 Read: Write: Reset: Bit 15 6 Bit 14 5 Bit 13 Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
Indeterminate after Reset 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Register Name and Address TACH5H -- $0036
Indeterminate after Reset
Register Name and Address TACH5L -- $0037 Bit 7 Read: Write: Reset: Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
Indeterminate after Reset
Figure 23-9. TIMA Channel Registers (TACH0H/L-TACH5H/L) (Sheet 2 of 2)
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Advance Information -- MC68HC08AZ60A
Section 24. Analog-to-Digital Converter (ADC-15)
24.1 Contents
24.2 24.3 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
24.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .434 24.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 24.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 24.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 24.4.4 Continuous Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . 437 24.4.5 Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . 437 24.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
24.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 24.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 24.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 24.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 24.7.1 ADC Analog Power Pin (VDDAREF) . . . . . . . . . . . . . . . . 438 24.7.2 ADC Analog Ground/ADC Voltage Reference Low Pin (AVSS/VREFL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 24.7.4 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . 439 24.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 24.8.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . 439 24.8.2 ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 24.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . 442
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Analog-to-Digital Converter (ADC-15)
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Analog-to-Digital Converter (ADC-15) 24.2 Introduction
This section describes the analog-to-digital converter. The ADC is an 8bit analog-to-digital converter. For further information regarding analog-to-digital converters on Motorola microcontrollers, please consult the HC08 ADC Reference Manual, ADCRM/AD.
24.3 Features
Features of the ADC module include: * * * * * * 15 Channels with Multiplexed Input Linear Successive Approximation 8-Bit Resolution Single or Continuous Conversion Conversion Complete Flag or Conversion Complete Interrupt Selectable ADC Clock
24.4 Functional Description
Fifteen ADC channels are available for sampling external sources at pins PTD6/ATD14/TACLK-PTD0/ATD8 and PTB7/ATD7-PTB0/ATD0. An analog multiplexer allows the single ADC converter to select one of 15 ADC channels as ADC voltage in (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. See Figure 24-1.
Advance Information 434 Analog-to-Digital Converter (ADC-15)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Analog-to-Digital Converter (ADC-15) Functional Description
INTERNAL DATA BUS READ DDRB/DDRB WRITE DDRB/DDRD RESET WRITE PTB/PTD DDRBx/DDRDx PTBx/PTDx DISABLE
PTBx/PTDx ADC CHANNEL x
READ PTB/PTD
DISABLE ADC DATA REGISTER
INTERRUPT LOGIC
CONVERSION COMPLETE
ADC
ADC VOLTAGE IN ADCVIN
CHANNEL SELECT
ADCH[4:0]
AIEN
COCO ADC CLOCK CGMXCLK BUS CLOCK
CLOCK GENERATOR
ADIV[2:0]
ADICLK
Figure 24-1. ADC Block Diagram
24.4.1 ADC Port I/O Pins PTD6/ATD14/TACLK-PTD0/ATD8 and PTB7/ATD7-PTB0/ATD0 are general-purpose I/O pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the
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Analog-to-Digital Converter (ADC-15)
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.
NOTE:
Do not use ADC channels ATD14 or ATD12 when using the PTD6/ATD14/TACLK or PTD4/ATD12/TBCLK pins as the clock inputs for the 16-bit Timers.
24.4.2 Voltage Conversion When the input voltage to the ADC equals VREFH (see Electrical Specifications on page 445), the ADC converts the signal to $FF (full scale). If the input voltage equals AVSS/VREFL, the ADC converts it to $00. Input voltages between VREFH and AVSS/VREFL are a straight-line linear conversion. Conversion accuracy of all other input voltages is not guaranteed. Avoid current injection on unused ADC inputs to prevent potential conversion error.
NOTE:
Input voltage should not exceed the analog supply voltages.
24.4.3 Conversion Time Conversion starts after a write to the ADSCR (ADC status control register, $0038), and requires between 16 and 17 ADC clock cycles to complete. Conversion time in terms of the number of bus cycles is a function of ADICLK select, CGMXCLK frequency, bus frequency, and ADIV prescaler bits. For example, with a CGMXCLK frequency of 4 MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz, one conversion will take between 16 and 17 s and there will be between 128 bus cycles between each conversion. Sample rate is approximately 60 kHz. Refer to Electrical Specifications on page 445. 16 to 17 ADC Clock Cycles Conversion Time = ADC Clock Frequency Number of Bus Cycles = Conversion Time x Bus Frequency
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Analog-to-Digital Converter (ADC-15) Interrupts
24.4.4 Continuous Conversion In the continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO bit is set after the first conversion and will stay set for the next several conversions until the next write of the ADC status and control register or the next read of the ADC data register.
24.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. See Electrical Specifications on page 445 for accuracy information.
24.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic 0. If the COCO bit is set, an interrupt is generated. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
24.6 Low-Power Modes
The following subsections describe the low-power modes.
24.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the WAIT instruction.
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Analog-to-Digital Converter (ADC-15)
24.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before attempting a new ADC conversion after exiting stop mode.
24.7 I/O Signals
The ADC module has 15 channels that are shared with I/O ports B and D. Refer to Electrical Specifications on page 445 for voltages referenced below.
24.7.1 ADC Analog Power Pin (VDDAREF) The ADC analog portion uses VDDAREF as its power pin. Connect the VDDAREF pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAREF for good results.
NOTE:
Route VDDAREF carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. VDDAREF must be present for operation of the ADC.
24.7.2 ADC Analog Ground/ADC Voltage Reference Low Pin (AVSS/VREFL) The ADC analog portion uses AVSS/VREFL as its ground pin. Connect the AVSS/VREFL pin to the same voltage potential as VSS. VREFL is the lower reference supply for the ADC.
24.7.3 ADC Voltage Reference Pin (VREFH) VREFH is the high reference voltage for all analog-to-digital conversions.
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Analog-to-Digital Converter (ADC-15) I/O Registers
24.7.4 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the 15 ADC channels to the ADC module.
24.8 I/O Registers
These I/O registers control and monitor ADC operation: * * * ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADICLK)
24.8.1 ADC Status and Control Register The following paragraphs describe the function of the ADC status and control register.
Address: $0038 Bit 7 Read: Write: Reset: COCO AIEN R 0 R 0 = Reserved 0 1 1 1 1 1 ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 6 5 4 3 2 1 Bit 0
Figure 24-2. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written or whenever the ADC data register is read.
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Advance Information 439
Analog-to-Digital Converter (ADC-15)
If the AIEN bit is a logic 1, the COCO is a read/write bit which selects the CPU to service the ADC interrupt request. Reset clears this bit. 1 = conversion completed (AIEN = 0) 0 = conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion ADCH[4:0] -- ADC Channel Select Bits ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of 15 ADC channels. Channel selection is detailed in the following table. Care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. See Table 24-1. The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows for reduced power consumption for the MCU when the ADC is not used. Reset sets these bits.
NOTE:
Recovery from the disabled state requires one conversion cycle to stabilize.
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Analog-to-Digital Converter (ADC-15) I/O Registers
Table 24-1. Mux Channel Select
ADCH4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 ADCH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 ADCH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 ADCH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Input Select PTB0/ATD0 PTB1/ATD1 PTB2/ATD2 PTB3/ATD3 PTB4/ATD4 PTB5/ATD5 PTB6/ATD6 PTB7/ATD7 PTD0/ATD8 PTD1/ATD9 PTD2/ATD10 PTD3/ATD11 PTD4/ATD12/TBCLK PTD5/ATD13 PTD6/ATD14/TACLK Unused (see Note 1) Range 01111 ($0F) to 11010 ($1A) Unused (see Note 1) 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 Reserved Unused (see Note 1) VREFH (see Note 2) AVSS/VREFL (see Note 2) [ADC power off]
NOTES: 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications.
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Analog-to-Digital Converter (ADC-15)
24.8.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $0039 Bit 7 Read: Write: Reset: R = Reserved AD7 R 6 AD6 R 5 AD5 R 4 AD4 R 3 AD3 R 2 AD2 R 1 AD1 R Bit 0 AD0 R
Indeterminate after Reset
Figure 24-3. ADC Data Register (ADR)
24.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC.
Address: $003A Bit 7 Read: ADIV2 Write: Reset:
0
6 ADIV1 0 = Reserved
5 ADIV0 0
4 ADICLK
3 0 R
2 0 R 0
1 0 R 0
Bit 0 0 R 0
0
0
R
Figure 24-4. ADC Input Clock Register (ADICLK) ADIV2-ADIV0 -- ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 242 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz.
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Analog-to-Digital Converter (ADC-15) I/O Registers
Table 24-2. ADC Clock Divide Ratio
ADIV2 0 0 0 0 1 ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate ADC Input Clock /1 ADC Input Clock / 2 ADC Input Clock / 4 ADC Input Clock / 8 ADC Input Clock / 16
X = don't care
ADICLK -- ADC Input Clock Register Bit ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. See Electrical Specifications on page 445. 1 = Internal bus clock 0 = External clock (CGMXCLK) fXCLK or Bus Frequency 1 MHz = ADIV[2:0]
NOTE:
During the conversion process, changing the ADC clock will result in an incorrect conversion.
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Advance Information 443
Analog-to-Digital Converter (ADC-15)
Advance Information 444 Analog-to-Digital Converter (ADC-15)
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Advance Information -- MC68HC08AZ60A
Section 25. Electrical Specifications
25.1 Contents
25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . 447 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 5.0 Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . 448 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 5.0 Vdc 0.5 V Serial Peripheral Interface (SPI) Timing . . 452 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 455
25.10 CGM Component Information . . . . . . . . . . . . . . . . . . . . . . . 456 25.11 CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . 457 25.12 RAM Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . 458 25.13 EEPROM Memory Characteristics . . . . . . . . . . . . . . . . . . .458 25.14 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 459 25.14.1 64-pin Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . .459
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Advance Information 445
Electrical Specifications 25.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate at the maximum ratings. Refer to 5.0 Volt DC Electrical Characteristics for guaranteed operating conditions. Table 25-1
Rating Supply Voltage Input Voltage Maximum Current Per Pin Excluding VDD and VSS Storage Temperature Maximum Current out of VSS Maximum Current into VDD Reset and IRQ Input Voltage NOTE: Voltages are referenced to VSS. Symbol VDD VIN I TSTG IMVSS IMVDD VHI Value -0.3 to +6.0 VSS -0.3 to VDD +0.3 Unit V V mA
25
-55 to +150 100 100 VDD + 4.5
C
mA mA V
NOTE:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD).
Advance Information 446 Electrical Specifications
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Electrical Specifications Functional Operating Range
25.3 Functional Operating Range
Table 25-2
Rating Operating Temperature Range(1) Operating Voltage Range
1. TA (MAX) = 125C for part suffix MFU 105C for part suffix VFU 85C for part suffix CFU
Symbol TA VDD
Value -40 to TA (max) 5.0 0.5v
Unit
C
V
NOTE:
For applications which use the LVI, Motorola guarantee the functionality of the device down to the LVI trip point (VLVI) within the constraints outlined in Low Voltage Inhibit (LVI) on page 195.
25.4 Thermal Characteristics
Table 25-3
Characteristic Thermal Resistance QFP (64 Pins) I/O Pin Power Dissipation Power Dissipation (see Note 1) Symbol Value 70 User Determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C PD x (TA + 273 C) + (PD2 x JA) TA = PD Unit
JA
PI/O PD
C/W
W W
Constant (see Note 2) Average Junction Temperature
K TJ
W/C
x JA
C
NOTES: 1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined from a known TA and measured PD. With this value of K, PD, and TJ can be determined for any value of TA.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Electrical Specifications
Advance Information 447
Electrical Specifications 25.5 5.0 Volt DC Electrical Characteristics
Table 25-4
Characteristic Output High Voltage (ILOAD = -2.0 mA) All Ports (ILOAD = -5.0 mA) All Ports Total source current Output Low Voltage (ILOAD = 1.6 mA) All Ports (ILOAD = 10.0 mA) All Ports Total sink current Input High Voltage All Ports, IRQs, RESET, OSC1 Input Low Voltage All Ports, IRQs, RESET, OSC1 VDD + VDDA Supply Current Run (see Note 2)(see Note 9) Wait (see Note 3)(see Note 9) Stop (see Note 4) 25 C -40 C to +125 C 25 C with LVI Enabled -40 C to +125 C with LVI Enabled I/O Ports Hi-Z Leakage Current I/O Ports Hi-Z Leakage Current (see Note 11) Input Current Input Current (see Note 11) Capacitance Ports (As Input or Output) Low-Voltage Reset Inhibit (trip) (recover) -- VOL -- IOL(TOT) VIH VIL -- 0.7 x VDD VSS 1.5 15 VDD 0.3 x VDD V mA V V 0.4 V VOH IOH(TOT) VDD -0.8 VDD -1.5 -- -- -- 10 V V mA Symbol Min Max Unit
-- -- IDD -- -- -- -- -1 -10 -1 -10 -- -- 3.80
35 20 50 100 400 500 1 10 1 10 12 8 4.49
mA mA
A A A A A A A A
pF V mV mV
IL IL IIN IIN COUT CIN VLVI VPOR VPORRST
POR ReArm Voltage (see Note 5) POR Reset Voltage (see Note 6)
0 0
200 800
Advance Information 448 Electrical Specifications
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Electrical Specifications Control Timing
Table 25-4
POR Rise Time Ramp Rate (see Note 7) High COP Disable Voltage (see Note 8) Monitor Mode Entry Voltage on IRQ (see Note 10) RPOR VHI VHI 0.02 TBD TBD -- TBD TBD V/ms V V
1.VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, TA = -40 C to TA (MAX), unless otherwise noted. 2.Run (Operating) IDD measured using external square wave clock source (fBUS = 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 3.Wait IDD measured using external square wave clock source (fBUS = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with all modules enabled. 4.Stop IDD measured with OSC1 = VSS. 5.Maximum is highest voltage that POR is guaranteed. 6.Maximum is highest voltage that POR is possible. 7.If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8.See Computer Operating Properly (COP) on page 189. VHI applied to RST. 9.Although IDD is proportional to bus frequency, a current of several mA is present even at very low frequencies. 10.See monitor mode description within Computer Operating Properly (COP) on page 189. VHI applied to IRQ or RST. 11.When subjected to a Human Body Model (HBM) ESD event as specified in AEC Q100-002 these pins may exhibit recoverable leakage values within the specification indicated.
25.6 Control Timing
Table 25-5
Characteristic Bus Operating Frequency (4.5-5.5 V -- VDD Only) Internal Clock Period (1/fBUS) RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period 16-Bit Timer Input Capture Pulse Width (see Note 2) Input Capture Period Input Clock Pulse Width MSCAN Wake-up Filter Pulse Width (see Note 4) Symbol fBUS tcyc tRL tILHI tILIL tTH, tTL tTLTL tTCH, tTCL tWUP Min -- 119 1.5 1.5 Note 3 Max 8.4 -- -- -- -- Unit MHz ns tcyc tcyc tcyc tcyc tcyc ns
2 Note 3 (1/fOP) + 5 2
-- -- -- 5
s
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Advance Information 449
Electrical Specifications
Table 25-5
Characteristic Symbol Min Max Unit
1.VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, TA = -40 C to TA (MAX), unless otherwise noted. 2.Refer to Table 18-2 and Table 23-2 and supporting notes. 3.The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt service routine plus tcyc. 4. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested.
Advance Information 450 Electrical Specifications
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Electrical Specifications ADC Characteristics
25.7 ADC Characteristics
Table 25-6
Characteristic Resolution Absolute Accuracy (VREFL = 0 V, VDDA = VREFH = 5 V 0.5v) Conversion Range (see Note 1) Power-Up Time Input Leakage (see Note 3) Ports B and D Input Leakage (see Note 4) Ports B and D Conversion Time Monotonicity Zero Input Reading Full-Scale Reading Sample Time (see Note 2) Input Capacitance ADC Internal Clock Analog Input Voltage 00 FE 5 -- 500 k VREFL Min 8 -1 VREFL 16 -1 - 10 Max 8 +1 VREFH 17 1 10 Unit Bits LSB V Includes Quantization VREFL = VSSA Conversion Time Period Comments
s A A
ADC Clock Cycles
16
17
Includes Sampling Time
Inherent within Total Error 01 FF -- 8 1.048 M VREFH Hex Hex ADC Clock Cycles pF Hz V Not Tested Tested Only at 1 MHz VIN = VREFL VIN = VREFH
1.VDD = 5.0 Vdc 0.5v, VSS = 0 Vdc, VDDA/VDDAREF = 5.0 Vdc 0.5v, VSSA = 0 Vdc, VREFH = 5.0 Vdc 0.5v 2.Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 3.The external system error caused by input leakage current is approximately equal to the product of R source and input current. 4.When subjected to a Human Body Model (HBM) ESD event as specified in AEC Q100-002 these pins may exhibit recoverable leakage values within the specification indicated.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Electrical Specifications
Advance Information 451
Electrical Specifications 25.8 5.0 Vdc 0.5 V Serial Peripheral Interface (SPI) Timing
Table 25-7
Num Characteristic Operating Frequency (see Note 3) Master Slave 1 2 3 4 Cycle Time Master Slave Enable Lead Time Enable Lag Time Clock (SCK) High Time Master Slave Clock (SCK) Low Time Master Slave Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Access Time, Slave (see Note 4) CPHA = 0 CPHA = 1 Slave Disable Time (Hold Time to High-Impedance State) Enable Edge Lead Time to Data Valid (see Note 6) Master Slave Data Hold Time (Outputs, after Enable Edge) Master Slave Data Valid Master (Before Capture Edge) Data Hold Time (Outputs) Master (After Capture Edge) Symbol fBUS(M) fBUS(S) tcyc(M) tcyc(S) tLead tLag tW(SCKH)M tW(SCKH)S tW(SCKL)M tW(SCKL)S tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS tEV(M) tEV(S) tHO(M) tHO(S) tV(M) tHO(M) Min fBUS/128 dc 2 1 15 15 100 50 100 50 45 5 0 15 0 0 -- -- -- 0 5 90 100 Max fBUS/2 fBUS 128 -- -- -- -- -- -- -- -- -- -- -- 40 20 25 10 40 -- -- -- -- Unit MHz
tcyc ns ns ns
5
ns
6
ns
7
ns
8 9 10
ns ns ns
11 12 13
ns ns ns
NOTES: 1. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins. 2. Item numbers refer to dimensions in Figure 25-1 and Figure 25-2. 3. fBUS = the currently active bus frequency for the microcontroller. 4. Time to data active from high-impedance state. 5. With 100 pF on all SPI pins
Advance Information 452 Electrical Specifications
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Electrical Specifications 5.0 Vdc 0.5 V Serial Peripheral Interface (SPI) Timing
SS (INPUT)
SS pin of master held high. 1
SCK (CPOL = 0) (OUTPUT)
NOTE
5 4
SCK (CPOL = 1) (OUTPUT)
NOTE
5 4 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT
MISO (INPUT) 10 MOSI (OUTPUT)
MSB IN 11 MASTER MSB OUT 12 13
BITS 6-1
NOTE: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS (INPUT)
SS pin of master held high. 1
SCK (CPOL = 0) (OUTPUT)
5 4
NOTE
SCK (CPOL = 1) (OUTPUT)
5 4 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT
NOTE
MISO (INPUT) 10 MOSI (OUTPUT)
MSB IN 11 MASTER MSB OUT 12 13
BITS 6-1
NOTE: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 25-1. SPI Master Timing Diagram
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Electrical Specifications
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (INPUT) SLAVE 6 MOSI (OUTPUT) MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN SLAVE LSB OUT 11 5 4 9 NOTE 11 5 4 3
NOTE: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) 5 4 10 NOTE SLAVE 6 MOSI (INPUT) MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN 9 SLAVE LSB OUT 5 4 3
NOTE: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 25-2. SPI Slave Timing Diagram
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Electrical Specifications CGM Operating Conditions
25.9 CGM Operating Conditions
Characteristic Operating Voltage VSSA Crystal Reference Frequency Module Crystal Reference Frequency Range Nom. Multiplier VCO Center-of-Range Frequency VCO Operating Frequency fCGMRCLK fCGMXCLK fNOM fCGMVRS fCGMVCLK VSS-0.3 1 -- -- 4.9152 4.9152 -- 4.9152 4.9152 4.9152 -- -- VSS+0.3 16 -- -- Note 1 32.0 V MHz MHz MHz MHz MHz Same Frequency as fCGMRCLK Symbol VDDA Min VDD-0.3 Typ -- Max VDD+0.3 Unit V Comments
1. fCGMVRS is a nominal value described and calculated as an example in the Clock Generator Module (CGM) section for the desired VCO operating frequency, fCGMVCLK.
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Electrical Specifications 25.10 CGM Component Information
Description Crystal Load Capacitance Crystal Fixed Capacitance Crystal Tuning Capacitance Filter Capacitor Multiply Factor Symbol CL C1 C2 CFACT CF Min -- -- -- -- Typ -- 2 x CL 2 x CL 0.0154 CFACT x (VDDA/ fCGMXCLK) Max -- -- -- -- Unit -- -- -- F/s V See External Filter -- --
Capacitor Pin (CGMXFC)
Comments Consult Crystal Manufacturer's Data Consult Crystal Manufacturer's Data Consult Crystal Manufacturer's Data
Filter Capacitor
--
on page 151. CBYP must provide low AC impedance from f = fCGMXCLK/100 to 100 x fCGMVCLK, so series resistance must be considered.
Bypass Capacitor
CBYP
--
0.1 F
--
F
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Electrical Specifications CGM Acquisition/Lock Time Information
25.11 CGM Acquisition/Lock Time Information
Description Manual Mode Time to Stable Symbol tACQ tAL tLOCK DTRK DUNT DLOCK DUNL nACQ Min -- Typ (8 x VDDA) / (fCGMXCLK x KACQ) (4 x VDDA) / (fCGMXCLK x KTRK) tACQ+tAL -- -- -- -- 32 Max -- Unit s Notes If CF Chosen Correctly If CF Chosen Correctly
Manual Stable to Lock Time Manual Acquisition Time Tracking Mode Entry Frequency Tolerance Acquisition Mode Entry Frequency Tolerance LOCK Entry Freq. Tolerance LOCK Exit Freq. Tolerance Reference Cycles per Acquisition Mode Measurement Reference Cycles per Tracking Mode Measurement Automatic Mode Time to Stable Automatic Stable to Lock Time Automatic Lock Time PLL Jitter, Deviation of Average Bus Frequency over 2 ms (note 1) K value for automatic mode time to stable K value
-- -- 0
-- --
s s % % % % --
3.6 7.2 0.9 1.8
--
6.3
0
0.9
--
nTRK
-- nACQ/fCGM
XCLK
128 (8 x VDDA) / (fCGMXCLK x KACQ) (4 x VDDA) / (fCGMXCLK x KTRK) 0.65 --
--
-- If CF Chosen Correctly If CF Chosen Correctly
tACQ tAL tLOCK
s
nTRK/fCGM
XCLK
-- 25
s ms %
-- 0
(fCRYS) x (.025%) x (N/4)
-- --
N = VCO Freq. Mult.
Kacq Ktrk
-- --
0.2 0.004
-- --
NOTES: 1. Guaranteed but not tested. 2. VDD = 5.0 Vdc 0.5 V, VSS = 0 Vdc, TA = -40C to TA (MAX), unless otherwise noted. 3. Conditions for typical and maximum values are for Run mode with fCGMXCLK = 8MHz, fBUSDES = 8MHz, N = 4, L = 7, discharged CF = 15 nF, VDD = 5Vdc. 4. Refer to Phase-Locked Loop (PLL) section for guidance on the use of the PLL.
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Electrical Specifications 25.12 RAM Memory Characteristics
Table 25-3.
Characteristic RAM Data Retention Voltage Symbol VRDR Min 0.7 Max -- Unit V
25.13 EEPROM Memory Characteristics
Table 25-4.
Characteristic EEPROM Programming Time per Byte EEPROM Erasing Time per Byte EEPROM Erasing Time per Block EEPROM Erasing Time per Bulk EEPROM Programming Voltage Discharge Period Number of Programming Operations to the Same EEPROM Byte Before Erase (1) EEPROM Write/Erase Cycles @ 10 ms Write Time EEPROM Data Retention After 10,000 Write/Erase Cycles EEPROM Programming Maximum Time to `AUTO' Bit Set EEPROM Erasing Maximum Time to `AUTO' Bit Set
NOTES: 1. Programming a byte more times than the specified maximum may affect the data integrity of that byte. The byte must be erased before it can be programmed again.
Symbol tEEPGM tEEBYTE tEEBLOCK tEEBULK tEEFPV -- -- -- -- --
Min 10 10 10 10 100 -- 10,000 10 -- --
Max -- -- -- -- -- 8 -- -- 500 8
Unit ms ms ms ms
s
-- Cycles Years
s
ms
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Electrical Specifications Mechanical Specifications
25.14 Mechanical Specifications
25.14.1 64-pin Quad Flat Pack (QFP)
L
48 49 33 0.20 M C A - B S D S 0.20 M H A - B S D S 32 B B P
- A, B, D Detail "A" F
-AL
-BB
Detail "A" 64 1 -DA 0.20 M C A - B S D S 0.05 A - B S 0.20 M H A - B S D S Detail "C" E M D Section B-B 0.20 M C A - B S D S Base Metal 16 17 J N
0.05 A - B
V
U
T R Q
C -CSeating Plane H G M
Datum -H- Plane
K W X
Dim. A B C D E F G H J K L
Min. 13.90 13.90 2.15 0.30 2.00 0.30 -- 0.13 0.65
Max. 14.10 14.10 2.45 0.45 2.40 0.40 0.25 0.23 0.95
Notes
1. Datum Plane -H- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. Datums A-B and -D to be determined at Datum Plane -H-. 3. Dimensions S and V to be determined at seating plane -C-. 4. Dimensions A and B do not include mould protrusion. Allowable mould protrusion is 0.25mm per side. Dimensions A and B do include mould mismatch and are determined at Datum Plane -H-. 5. Dimension D does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 total in excess of the D dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 6. Dimensions and tolerancing per ANSI Y 14.5M, 1982. 7. All dimensions in mm.
Dim. M N P Q R S T U V W X
Min. 5 0.13 0 0.13 16.95 0.13 0 16.95 0.35
Max. 10 0.17 7 0.30 17.45 -- -- 17.45 0.45
0.40 BSC
0.80 BSC
12.00 REF
1.6 REF
Figure 25-5. 64-pin QFP (Case #840B)
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Electrical Specifications
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Section 26. MC68HC08AZ60A Changes
26.1 Contents
Significant Changes from the MC68HC08AZ60 (Non-A Suffix Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 26.2.1 Monitor ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 26.2.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 26.2.3 Mask Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . .462 26.2.4 Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . 463 26.2
26.2 Significant Changes from the MC68HC08AZ60 (Non-A Suffix Device)
26.2.1 Monitor ROM The monitor ROM is now allocated 320 bytes within the memory map though not all that space is necessarily used. Functionality of the monitor ROM is unchanged.
26.2.2 EEPROM 26.2.2.1 EEPROM Architecture The EEPROM-1 and EEPROM-2 are made from a new NVM technology. However, the bit polarity remains the same i.e. programmed=0, erased=1. 26.2.2.2 EEPROM Clock Source and Pre-scaler The first major difference on the new EEPROM is that it requires a constant time base source to ensure secure programming and erase operations. This is done by firstly selecting which clock source is going
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MC68HC08AZ60A Changes
to drive the EExDIV clock divider inputs using bit 7 of the new MORB mask option register $FE09. Next the divide ratio from this source has to be set by programming an 11-bit time base pre-scalar into bits spread over two new registers, EExDIVH and EExDIVL (where x=1 or 2 for EEPROM-1 and EEPROM-2 arrays). The EExDIVH and EExDIVL registers are volatile. However, they are loaded upon reset by the contents of duplicate non-volatile EExDIVHNVR and EExDIVLNVR registers much in the same way as the array control registers (EExACR) interacts with the non-volatile registers (EExNVR) for configuration control on the existing revision. As a result of the new EEDIV clock described above, bit 7 (EEBCLK) of the EEPROM control registers (EExCR) is no longer used. 26.2.2.3 EEPROM AUTO Programming & Erasing The second major change to the EEPROM is the inclusion in the EEPROM control registers (EExCR) of an AUTO function using previously unused bit 1 of that register. The AUTO function enables the logic of the MCU to automatically use the optimum programming or erasing time for the EEPROM. If using AUTO the user does not need to wait for the normal minimum specified programming or erasing time. After setting the EEPGM bit as normal the user just has to poll that bit again, waiting for the MCU to clear it indicating that programming or erasing is complete.
26.2.3 Mask Option Registers 26.2.3.1 Mask Option Register B A new mask option register B (MORB) has been introduced for the Asuffix silicon. This contains two user-selectable bits and one fixed bit. Bit 3 is a silicon hard set bit, which identifies this new A-suffix silicon. Bit 4 is a bit that can enable EEPROM-1 and EEPROM-2 read protection when in monitor mode.
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MC68HC08AZ60A Changes Significant Changes from the MC68HC08AZ60 (Non-A Suffix Device)
Bit 7 is an EEPROM time base divider clock select bit selecting the reference clock source for the EEPROM time base divider module (refer to EEPROM changes described above).
26.2.4 Low-Voltage Inhibit (LVI) The Low-Voltage Inhibit (LVI) specifications for trip and recovery voltage (VLVI) have been altered based upon module performance on silicon. Please see for Electrical Specifications details.
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MC68HC08AZ60A Changes
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Section 27. MC68HC08AZ48A Memory Map
27.1 Contents
27.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
27.2 Introduction
The MC68HC08AZ48A is basically identical to the MC68HC08AZ60A part except that ROM, RAM and EEPROM sizes are smaller. The memory map, shown in Figure 27-1, includes: * * * * * 48,640 Bytes of ROM 1536 Bytes of RAM 768 Bytes of EEPROM with Protect Option 52 Bytes of User-Defined Vectors 256 Bytes of Monitor ROM
The following definitions apply to the memory map representation of reserved and unimplemented locations. * * Reserved -- Accessing a reserved location can have unpredictable effects on MCU operation. Unused -- These locations are reserved in the memory map for future use, accessing an unused location can have unpredictable effects on MCU operation. Unimplemented -- Accessing an unimplemented location can cause an illegal address reset (within the constraints as outlined in the System Integration Module (SIM)).
*
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MC68HC08AZ48A Memory Map
MC68HC08AZ48A
$0000 $004F $0050 $044F $0450 $04FF $0500 $057F $0580 $05FF $0600 $06FF $0700 $07FF $0800 $09FF $0A00 $0BFF $0C00 $3FFF $4000 $7FFF $8000 $FDFF $FE00 $FE01 I/O REGISTERS (80 BYTES)
RAM-1, 1024 BYTES
RESERVED (176 BYTES)
CAN CONTROL AND MESSAGE BUFFERS, 128 BYTES
RESERVED (128 BYTES)
EEPROM-2, 256BYTES
RESERVED (256 BYTES)
EEPROM-1, 512 BYTES
RAM-2 , 512 BYTES
RESERVED (13,312 BYTES)
ROM-2, 16,384 BYTES
ROM-1, 32,256BYTES SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR)
Advance Information 466 MC68HC08AZ48A Memory Map
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MC68HC08AZ48A Memory Map Introduction
MC68HC08AZ48A
$FE02 $FE03 $FE04 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FE11 $FE12 $FE19 $FE1A $FE1B $FE1C $FE1D $FE1E $FE1F $FE20 $FF1F $FF20 $FF6F $FF70 $FF71 RESERVED SIM BREAK FLAG CONTROL REGISTER (SBFCR) RESERVED (5 BYTES) MASK OPTION REGISTER B (MORB) RESERVED RESERVED BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BSCR) LVI STATUS REGISTER (LVISR) EEPROM-1EEDIVH NON-VOLATILE REGISTER (EE1DIVHNVR) EEPROM-1EEDIVL NON-VOLATILE REGISTER (EE1DIVLNVR) RESERVED (8 BYTES) EEPROM-1 EE DIVIDER HIGH REGISTER (EE1DIVH) EEPROM-1 EE DIVIDER LOW REGISTER (EE1DIVL) EEPROM-1 EEPROM NON-VOLATILE REGISTER (EE1NVR) EEPROM-1 EEPROM CONTROL REGISTER (EE1CR) RESERVED EEPROM-1 EEPROM ARRAY CONFIGURATION REGISTER (EE1ACR) MONITOR ROM (256BYTES)
UNIMPLEMENTED (80 BYTES) EEPROM-2 EEDIVH NON-VOLATILE REGISTER (EE2DIVHNVR) EEPROM-2 EEDIVL NON-VOLATILE REGISTER (EE2DIVLNVR)
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MC68HC08AZ48A Memory Map
MC68HC08AZ48A
$FF72 $FF79 $FF7A $FF7B $FF7C $FF7D $FF7E $FF7F $FF80 $FFCB $FFCC $FFFF RESERVED (8 BYTES) EEPROM-2 EE DIVIDER HIGH REGISTER (EE2DIVH) EEPROM-2 EE DIVIDER LOW REGISTER (EE2DIVL) EEPROM-2 EEPROM NON-VOLATILE REGISTER (EE2NVR) EEPROM-2 EEPROM CONTROL REGISTER (EE2CR) RESERVED EEPROM-2 EEPROM ARRAY CONFIGURATION REGISTER (EE2ACR) RESERVED (76 BYTES)
VECTORS (52BYTES)
Figure 27-1. Memory Map (Continued)
Advance Information 468 MC68HC08AZ48A Memory Map
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Glossary
A -- See "accumulator (A)." accumulator (A) -- An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode -- A mode of PLL operation during startup before the PLL locks on a frequency. Also see "tracking mode." address bus -- The set of wires that the CPU or DMA uses to read and write memory locations. addressing mode -- The way that the CPU determines the operand address for an instruction. The M68HC08 CPU has 16 addressing modes. ALU -- See "arithmetic logic unit (ALU)." arithmetic logic unit (ALU) -- The portion of the CPU that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous -- Refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate -- The total number of bits transmitted per unit of time. BCD -- See "binary-coded decimal (BCD)." binary -- Relating to the base 2 number system. binary number system -- The base 2 number system, having two digits, 0 and 1. Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. binary-coded decimal (BCD) -- A notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. For example, 234 (decimal) = 0010 0011 0100 (BCD) bit -- A binary digit. A bit has a value of either logic 0 or logic 1.
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Glossary
branch instruction -- An instruction that causes the CPU to continue processing at a memory location other than the next sequential address. break module -- A module in the M68HC08 Family. The break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint -- A number written into the break address registers of the break module. When a number appears on the internal address bus that is the same as the number in the break address registers, the CPU executes the software interrupt instruction (SWI). break interrupt -- A software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus -- A set of wires that transfers logic signals. bus clock -- The bus clock is derived from the CGMOUT output from the CGM. The bus clock frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by four. byte -- A set of eight bits. C -- The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). CCR -- See "condition code register." central processor unit (CPU) -- The primary functioning unit of any computer system. The CPU controls the execution of instructions. CGM -- See "clock generator module (CGM)." clear -- To change a bit from logic 1 to logic 0; the opposite of set. clock -- A square wave signal used to synchronize events in a computer. clock generator module (CGM) -- A module in the M68HC08 Family. The CGM generates a base clock signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit and or phase-locked loop (PLL) circuit. comparator -- A device that compares the magnitude of two inputs. A digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (COP) -- A counter module in the M68HC08 Family that resets the MCU if allowed to overflow.
Advance Information 470 Glossary
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Glossary
condition code register (CCR) -- An 8-bit register in the CPU08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit -- One bit of a register manipulated by software to control the operation of the module. control unit -- One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations. The control unit decodes instructions and generates the internal control signals that perform the requested operations. The outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU registers, and bus interface. COP -- See "computer operating properly module (COP)." counter clock -- The input clock to the TIM counter. This clock is the output of the TIM prescaler. CPU -- See "central processor unit (CPU)." CPU08 -- The central processor unit of the M68HC08 Family. CPU clock -- The CPU clock is derived from the CGMOUT output from the CGM. The CPU clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by four. CPU cycles -- A CPU cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles. CPU registers -- Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are: * * * * * A (8-bit accumulator) H:X (16-bit index register) SP (16-bit stack pointer) PC (16-bit program counter)
CCR (condition code register containing the V, H, I, N, Z, and C bits) CSIC -- customer-specified integrated circuit cycle time -- The period of the operating frequency: tCYC = 1/fOP. decimal number system -- Base 10 numbering system that uses the digits zero through nine.
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Glossary
direct memory access module (DMA) -- A M68HC08 Family module that can perform data transfers between any two CPU-addressable locations without CPU intervention. For transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster and more code-efficient than CPU interrupts. DMA -- See "direct memory access module (DMA)." DMA service request -- A signal from a peripheral to the DMA module that enables the DMA module to transfer data. duty cycle -- A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is usually represented by a percentage. EEPROM -- Electrically erasable, programmable, read-only memory. A nonvolatile type of memory that can be electrically reprogrammed. EPROM -- Erasable, programmable, read-only memory. A nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception -- An event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program. external interrupt module (IRQ) -- A module in the M68HC08 Family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch -- To copy data from a memory location into the accumulator. firmware -- Instructions and data programmed into nonvolatile memory. free-running counter -- A device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission -- Communication on a channel in which data can be sent and received simultaneously. H -- The upper byte of the 16-bit index register (H:X) in the CPU08. H -- The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. The half-carry bit is required for binary-coded decimal arithmetic operations. The decimal adjust accumulator (DAA) instruction uses the state of the H and C bits to determine the appropriate correction factor. hexadecimal -- Base 16 numbering system that uses the digits 0 through 9 and the letters A through F. high byte -- The most significant eight bits of a word.
Advance Information 472 Glossary
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Glossary
illegal address -- An address not within the memory map illegal opcode -- A nonexistent opcode. I -- The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts are disabled. index register (H:X) -- A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine the effective address of the operand. H:X can also serve as a temporary data storage location. input/output (I/O) -- Input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions -- Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction. interrupt -- A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request -- A signal from a peripheral to the CPU intended to cause the CPU to execute a subroutine. I/O -- See "input/output (I/0)." IRQ -- See "external interrupt module (IRQ)." jitter -- Short-term signal instability. latch -- A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency -- The time lag between instruction completion and data movement. least significant bit (LSB) -- The rightmost digit of a binary number. logic 1 -- A voltage level approximately equal to the input power voltage (VDD). logic 0 -- A voltage level approximately equal to the ground voltage (VSS). low byte -- The least significant eight bits of a word. low voltage inhibit module (LVI) -- A module in the M68HC08 Family that monitors power supply voltage.
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Glossary
LVI -- See "low voltage inhibit module (LVI)." M68HC08 -- A Motorola family of 8-bit MCUs. mark/space -- The logic 1/logic 0 convention used in formatting data in serial communication. mask -- 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used in integrated circuit fabrication to transfer an image onto silicon. mask option -- A optional microcontroller feature that the customer chooses to enable or disable. mask option register (MOR) -- An EPROM location containing bits that enable or disable certain MCU features. MCU -- Microcontroller unit. See "microcontroller." memory location -- Each M68HC08 memory location holds one byte of data and has a unique address. To store information in a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. To read information from a memory location, the CPU places the address of the location on the address bus and asserts the read signal. In response to the read signal, the selected memory location places its data onto the data bus. memory map -- A pictorial representation of all memory locations in a computer system. microcontroller -- Microcontroller unit (MCU). A complete computer system, including a CPU, memory, a clock oscillator, and input/output (I/O) on a single integrated circuit. modulo counter -- A counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor ROM -- A section of ROM that can execute commands from a host computer for testing purposes. MOR -- See "mask option register (MOR)." most significant bit (MSB) -- The leftmost digit of a binary number. multiplexer -- A device that can select one of a number of inputs and pass the logic level of that input on to the output. N -- The negative bit in the condition code register of the CPU08. The CPU sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble -- A set of four bits (half of a byte).
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MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Glossary
object code -- The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode -- A binary code that instructs the CPU to perform an operation. open-drain -- An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand -- Data on which an operation is performed. Usually a statement consists of an operator and an operand. For example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator -- A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. OTPROM -- One-time programmable read-only memory. A nonvolatile type of memory that cannot be reprogrammed. overflow -- A quantity that is too large to be contained in one byte or one word. page zero -- The first 256 bytes of memory (addresses $0000-$00FF). parity -- An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even parity system, every byte should have an even number of logic 1s. In the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts the number of logic 1s in each byte. The parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. PC -- See "program counter (PC)." peripheral -- A circuit not under direct CPU control. phase-locked loop (PLL) -- A oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal. PLL -- See "phase-locked loop (PLL)." pointer -- Pointer register. An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity -- The two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, VDD and VSS. polling -- Periodically reading a status bit to monitor the condition of a peripheral device. port -- A set of wires for communicating with off-chip devices.
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Glossary Advance Information 475
Glossary
prescaler -- A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program -- A set of computer instructions that cause a computer to perform a desired operation or operations. program counter (PC) -- A 16-bit register in the CPU08. The PC register holds the address of the next instruction or operand that the CPU will use. pull -- An instruction that copies into the accumulator the contents of a stack RAM location. The stack RAM address is in the stack pointer. pullup -- A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width -- The amount of time a signal is on as opposed to being in its off state. pulse-width modulation (PWM) -- Controlled variation (modulation) of the pulse width of a signal with a constant frequency. push -- An instruction that copies the contents of the accumulator to the stack RAM. The stack RAM address is in the stack pointer. PWM period -- The time required for one complete cycle of a PWM waveform. RAM -- Random access memory. All RAM locations can be read or written by the CPU. The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off. RC circuit -- A circuit consisting of capacitors and resistors having a defined time constant. read -- To copy the contents of a memory location to the accumulator. register -- A circuit that stores a group of bits. reserved memory location -- A memory location that is used only in special factory test modes. Writing to a reserved location has no effect. Reading a reserved location returns an unpredictable value. reset -- To force a device to a known condition. ROM -- Read-only memory. A type of memory that can be read but cannot be changed (written). The contents of ROM must be specified before manufacturing the MCU. SCI -- See "serial communication interface module (SCI)." serial -- Pertaining to sequential transmission over a single line.
Advance Information 476 Glossary
MC68HC08AZ60A -- Rev 0.0 MOTOROLA
Glossary
serial communications interface module (SCI) -- A module in the M68HC08 Family that supports asynchronous communication. serial peripheral interface module (SPI) -- A module in the M68HC08 Family that supports synchronous communication. set -- To change a bit from logic 0 to logic 1; opposite of clear. shift register -- A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed -- A binary number notation that accommodates both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the magnitude of the number. software -- Instructions and data that control the operation of a microcontroller. software interrupt (SWI) -- An instruction that causes an interrupt and its associated vector fetch. SPI -- See "serial peripheral interface module (SPI)." stack -- A portion of RAM reserved for storage of CPU register contents and subroutine return addresses. stack pointer (SP) -- A 16-bit register in the CPU08 containing the address of the next available storage location on the stack. start bit -- A bit that signals the beginning of an asynchronous serial transmission. status bit -- A register bit that indicates the condition of a device. stop bit -- A bit that signals the end of an asynchronous serial transmission. subroutine -- A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns to the main program where it left off. synchronous -- Refers to logic circuits and operations that are synchronized by a common reference signal. TIM -- See "timer interface module (TIM)."
MC68HC08AZ60A -- Rev 0.0 MOTOROLA Glossary
Advance Information 477
Glossary
timer interface module (TIM) -- A module used to relate events in a system to a point in time. timer -- A module used to relate events in a system to a point in time. toggle -- To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode -- Mode of low-jitter PLL operation during which the PLL is locked on a frequency. Also see "acquisition mode." two's complement -- A means of performing binary subtraction using addition techniques. The most significant bit of a two's complement number indicates the sign of the number (1 indicates negative). The two's complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered -- Utilizes only one register for data; new data overwrites current data. unimplemented memory location -- A memory location that is not used. Writing to an unimplemented location has no effect. Reading an unimplemented location returns an unpredictable value. Executing an opcode at an unimplemented location causes an illegal address reset. V --The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow bit. variable -- A value that changes during the course of program execution. VCO -- See "voltage-controlled oscillator." vector -- A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (VCO) -- A circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform -- A graphical representation in which the amplitude of a wave is plotted against time. wired-OR -- Connection of circuit outputs so that if any output is high, the connection point is high. word -- A set of two bytes (16 bits). write -- The transfer of a byte of data from the CPU to a memory location. X -- The lower byte of the index register (H:X) in the CPU08. Z -- The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00.
Advance Information 478 Glossary MC68HC08AZ60A -- Rev 0.0 MOTOROLA
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